G01R 31/31711
Evaluation methods
Official title: {Evaluation methods, e.g. shmoo plots}
G01R31/31711 (Evaluation methods) appears on 66 US grants and 79 published applications in this corpus.
Search patents in G01R- Granted patents
- 66
- Published applications
- 79
- Assignees
- 42
- Inventors
- 163
- Latest grant
- 14 Oct 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2000 | 1 | 0 |
| 2001 | 0 | 2 |
| 2002 | 1 | 0 |
| 2003 | 3 | 5 |
| 2004 | 4 | 5 |
| 2005 | 2 | 3 |
| 2006 | 2 | 5 |
| 2007 | 6 | 7 |
| 2008 | 0 | 4 |
| 2009 | 5 | 3 |
| 2010 | 3 | 6 |
| 2011 | 2 | 4 |
| 2012 | 4 | 1 |
| 2013 | 3 | 0 |
| 2014 | 5 | 4 |
| 2015 | 2 | 1 |
| 2016 | 2 | 3 |
| 2017 | 2 | 2 |
| 2018 | 1 | 3 |
| 2019 | 3 | 4 |
| 2020 | 5 | 2 |
| 2021 | 0 | 5 |
| 2022 | 3 | 4 |
| 2023 | 3 | 3 |
| 2024 | 3 | 1 |
| 2025 | 1 | 2 |
By publication year. Applications have been published since 2001.
Recent patents
- Circuit, chip and semiconductor device14 Oct 2025US 12,445,135 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Apparatus for performing multiple tests on a device under test31 Dec 2024US 12,181,515 B2Nanya Technology Corporation
- Bit error ratio estimation using machine learning19 Nov 2024US 12,146,914 B2Tektronix, Inc.
- Circuit, chip and semiconductor device25 Jun 2024US 12,021,537 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Identifying data valid windows14 Nov 2023US 11,815,554 B2Micron Technology, Inc.
- Jitter measurement circuit and jitter measurement method17 Apr 2025US 2025/0123327 A1Iucf-Hyu (Industry-University Cooperation Foundation Hanyang University)
- Eye-diagram index analytic method, computer readable recording medium, and electronic apparatus6 Mar 2025US 2025/0076379 A1Novatek Microelectronics Corp.
- Circuit, chip and semiconductor device12 Sep 2024US 2024/0305301 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method and apparatus of analyzing data, and storage medium14 Sep 2023US 2023/0288476 A1Changxin Memory Technologies, Inc.
- Appratus for performing multiple tests on a device under test15 Jun 2023US 2023/0184821 A1Nanya Technology Corporation
Most cited
By later US patents
- On-chip eye viewer architecture for highspeed transceivers33US 8,744,012 B1Altera Corporation · 2014
- Margin test methods and circuits20US 7,627,029 B2Rambus Inc. · 2009
- Testing and repair methodology for memories having redundancy13US 7,222,274 B2International Business Machines Corporation · 2007
- Method for generating a Shmoo plot contour for integrated circuit tester12US 6,079,038 ACredence Systems Corporation · 2000
- Techniques for testing an electronic system using in-line signal distortion11US 7,133,795 B1EMC Corporation · 2006