Testing and repair methodology for memories having redundancy

A method of testing and repairing integrated circuit chips having a total number of fuses for effecting repair of said integrated circuit, comprising:

• (a) selecting an integrated circuit chip on a wafer for testing;
• (b) selecting a test parameter for shmoo memory testing;
• (c) reserving a first number of said total number of fuses for use in repairing said memory array based on results of said set of tests and then testing a memory array on said selected integrated circuit chip with a set of standard memory tests and;
• (d), shmoo memory testing said memory array by incrementing, decrementing, or both incrementing and decrementing values of a test parameter until (i) a predetermined minimum or a predetermined maximum value of said test parameter is reached and that requires no more than a second number of said total number of fuses for use in repairing said memory array to operate at said predetermined minimum or said predetermined maximum value of said test parameter;
• (e) saving a first set of fuse data based on said standard memory testing of said memory array and saving a second set of fuse data based on said shmoo memory testing of said memory array;
• and
• (f) repeating steps (a) through (e) until all integrated circuit chips to be tested have been selected.