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US 12,445,135 B2Granted
Circuit, chip and semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChao Chieh Li, Chia-Chun Liao, Min-Shueh Yuan, Chih-Hsien Chang
Life of this patent
Estimating the term…
Abstract
A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.
Claims20
A circuit, comprising:
- a time-to-digital converter (TDC), configured to receive a first signal having an identification and a first frequency, and output a digital signal associated with the identification of the first signal;
- and
- an evaluation circuit, coupled to the TDC and coupled to a phase-locked loop (PLL) external to the circuit, the evaluation circuit being configured to evaluate the identification of the first signal based on a transition between a first voltage level and a second voltage level of the digital signal.
A phase-locked loop (PLL), comprising:
- a time-to-digital converter (TDC), configured to receive a first signal having a first frequency and an identification to generate a digital signal;
- an evaluation circuit, coupled to the TDC, the evaluation circuit being configured to generate a second signal according to the digital signal;
- and
- an output divider (OD), coupled to the evaluation circuit, the OD being configured to output a third signal having a second frequency associated with the identification.
1 more element
A circuit, comprising:
- a time-to-digital converter (TDC), configured to convert a clock signal into a digital signal;
- and
- an evaluation circuit, coupled to the TDC and coupled to a phase-locked loop (PLL) external to the circuit, the evaluation circuit being configured to determine a sampling point of a first signal edge and a sampling point of a second signal edge of the digital signal according to a binary code of the digital signal, and evaluate a duty cycle of the clock signal according to whether the sampling point of the first signal edge is greater than a product of a predetermined positive integer and the sampling point of the second signal edge, wherein one of the first signal edge and the second signal edge is a rising edge, the other of the first signal edge and the second signal edge is a falling edge, and the sampling point of the first signal edge is later than the sampling point of the second signal edge.
Dependencies are inferred from the claim text.