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US 12,021,537 B2Granted
Circuit, chip and semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChao Chieh Li, Chia-Chun Liao, Min-Shueh Yuan, Chih-Hsien Chang
Life of this patent
Estimating the term…
Abstract
A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.
Claims20
A circuit, comprising:
- a time-to-digital converter (TDC), configured to receive a first signal having an identification and a first frequency, and output a digital signal associated with the identification of the first signal, wherein the identification comprises a duty cycle indicative of an active time of the first signal in a period of the first signal;
- and
- an evaluation circuit, coupled to the TDC and coupled to a phase-locked loop (PLL) external to the circuit.
A phase-locked loop (PLL), comprising:
- a time-to-digital converter (TDC), configured to convert a first signal into a digital signal;
- an evaluation circuit, coupled to the TDC, the evaluation circuit being configured to evaluate an identification of the first signal according to the digital signal, and accordingly generate a second signal;
- and
- an output divider (OD), coupled to the evaluation circuit and coupled to a device under test (DUT) external to the PLL, wherein the OD is configured to receive the second signal from the evaluation circuit, divide a predetermined frequency by a parameter level indicated by the second signal, and accordingly generate an output signal to the DUT.
1 more element
A method for evaluating a duty cycle of a clock signal, comprising:
- utilizing a time-to-digital converter (TDC) to convert the clock signal into a digital signal;
- determining a sampling point of a first signal edge and a sampling point of a second signal edge of the digital signal according to a binary code of the digital signal, wherein one of the first signal edge and the second signal edge is a rising edge, and the other of the first signal edge and the second signal edge is a falling edge;
- and
- when the sampling point of the first signal edge is later than the sampling point of the second signal edge, determining if the sampling point of the first signal edge is greater than a product of a predetermined positive integer and the sampling point of the second signal edge;
- wherein when it is determined that the sampling point of the first signal edge is greater than the product, the duty cycle is evaluated to fall within a first range;
- when it is determined that the sampling point of the first signal edge is less than the product, the duty cycle is evaluated to fall within a second range different from the first range.
3 more elements
Dependencies are inferred from the claim text.