H10D 30/0618
Of lateral schottky gate fets having multiple independently-addressable gate electrodes
Official title: {of lateral Schottky gate FETs having multiple independently-addressable gate electrodes}
H10D30/0618 (Of lateral schottky gate fets having multiple independently-addressable gate electrodes) appears on 13 US grants and 3 published applications in this corpus.
Search patents in H10D- Granted patents
- 13
- Published applications
- 3
- Assignees
- 11
- Inventors
- 17
- Latest grant
- 29 May 2018
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 2 | 0 |
| 1994 | 3 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 2 | 0 |
| 1999 | 1 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 1 |
| 2004 | 0 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 0 |
| 2007 | 0 | 0 |
| 2008 | 0 | 1 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 0 |
| 2013 | 0 | 0 |
| 2014 | 0 | 0 |
| 2015 | 0 | 0 |
| 2016 | 0 | 0 |
| 2017 | 0 | 0 |
| 2018 | 1 | 1 |
By publication year. Applications have been published since 2001.
Recent patents
- Integrated circuit with NMOS and PMOS transistors having different threshold voltages through channel doping and gate material work function schemes29 May 2018US 9,985,029 B2Commissariat A L' Energie Atomique Et Aux Energies Alternatives
- MOSFET having Schottky gate and bipolar device30 Nov 1999US 5,994,725 AToyota Jidosha Kabushiki Kaisha
- Field effect transistor28 Jul 1998US 5,786,610 AMitsubishi Denki Kabushiki Kaisha
- Method of manufacturing a semiconductor device30 Jun 1998US 5,773,334 AToyota Jidosha Kabushiki Kaisha
- Method of manufacturing a dual field effect transistor1 Nov 1994US 5,360,755 AMitsubishi Denki Kabushiki Kaisha
- Integrated circuit comprising transistors having different threshold voltages25 Jan 2018US 2018/0026036 A1Commissariat à I' énergie atomique et aux énergies alternatives
- Method for Manufacturing a Compound Semiconductor Field Effect Transistor Having a Fin Structure, and Compound Semiconductor Field Effect Transistor Having a Fin Structure18 Sep 2008US 2008/0224183 A1
- Semiconductor integrated circuit device and method of fabricating the same18 Sep 2003US 2003/0173584 A1Fujitsu Quantum Devices Limited
Most cited
By later US patents
- Method of manufacturing a field effect transistor23US 4,892,835 AU. S. Philips Corporation · 1990
- Dual-gate Schottky barrier gate fet having an intermediate electrode and a method of making same20US 4,048,646 ANippon Electric Co., Ltd. · 1977
- Planar-type field-effect transistor having metallized-well electrodes and a method of fabrication of said transistor18US 4,482,907 AThomson-CSF · 1984
- Method of manufacturing a semiconductor device14US 3,951,708 ARCA Corporation · 1976
- Semiconductor device having overlapping conductor layers12US 5,252,843 AFujitsu Limited · 1993