Integrated circuit comprising transistors having different threshold voltages

An integrated circuit comprising:

• first to third nMOS transistors having different threshold voltages, and first to third pMOS transistors having different threshold voltages, said transistors being arranged on an insulating layer having a thickness at most equal to 50 nm, said transistors having respective gate stacks, said nMOS transistors having channel regions made of silicon subjected to tensile stress in their direction of conduction and/or said pMOS transistors having channel regions made of SiGe subjected to compressive stress in their direction of conduction;
• a first well arranged underneath the insulating layer underneath said nMOS transistors, a second well arranged underneath the insulating layer underneath said pMOS transistors;
• characterized in that:
• the first and the second wells have one and the same type of doping with one and the same concentration of dopant, said first well being biased to a first bias Gnds, said second well being biased to a second bias Vdds different from Gnds;
• at least two of said gate stacks of said nMOS transistors comprising one and the same gate material, at least two of said gate stacks of said nMOS transistors comprising gate materials having separate work functions, the work function difference between the materials of these two stacks bringing about a threshold voltage difference of a value of 2* DVT between two of said nMOS transistors, at least two of said gate stacks of said pMOS transistors comprising one and the same gate material, the work function difference between the materials of these two stacks bringing about a threshold voltage difference of a value of 2* DVT between two of said pMOS transistors, at least two of said gate stacks of said pMOS transistors comprising gate materials having separate work functions, at least one gate stack of one of said nMOS transistors having one and the same gate material as a gate stack of one of said pMOS transistors;
• said nMOS transistors having only two different channel doping configurations, said pMOS transistors having only two different channel doping configurations, a difference in channel doping configuration between two nMOS transistors bringing about a threshold voltage difference DVT, a difference in channel doping configuration between two pMOS transistors bringing about a threshold voltage difference DVT;
• the following equation being satisfied:
• Gp*Vdds−Gn*Gnds=Sn*|σn|+Sp*(|σp|−1.65*109)−VarCais+K
• With Gn the sensitivity of the threshold voltage of the nMOS transistors to the doping of the first well, Sn the sensitivity of the threshold voltage of the nMOS transistors to the tensile stress in their channel region, σn the amplitude of the tensile stress in the channel region of the nMOS transistors, Gp the sensitivity of the threshold voltage of the pMOS transistors to the doping of the second well, Sp the sensitivity of the threshold voltage of the pMOS transistors to the compressive stress in their channel region, σp the amplitude of the tensile stress in the channel region of the pMOS transistors, VarCais a threshold voltage shift dependent on the doping of the first and second wells, K=2*DVT if the various gate stacks of said nMOS and pMOS transistors comprise only two different gate material compositions;
• K=0 if the various gate stacks of said nMOS and pMOS transistors comprise at least three different gate material compositions.