Integrated circuit with NMOS and PMOS transistors having different threshold voltages through channel doping and gate material work function schemes

An integrated circuit comprising:

• first to third nMOS transistors having different threshold voltages, and first to third pMOS transistors having different threshold voltages, said transistors being arranged on an insulating layer having a thickness at most equal to 50 nm, and said transistors having respective gate stacks, where one or both of said nMOS transistors have channel regions made of silicon subjected to tensile stress in their direction of conduction and said pMOS transistors have channel regions made of SiGe subjected to compressive stress in their direction of conduction;
• and
• a first well arranged underneath the insulating layer underneath said nMOS transistors, a second well arranged underneath the insulating layer underneath said pMOS transistors, wherein
• the first and the second wells have one and the same type of doping with one and the same concentration of dopant, said first well being biased to a first bias Gnds, and said second well being biased to a second bias Vdds different from the first bias Gnds,
• at least a first pair of said gate stacks of said nMOS transistors comprise one and the same gate material, and at least a second pair of said gate stacks of said nMOS transistors comprise gate materials having separate work functions, the work function difference between the gate materials of said at least the second pair of said gate stacks bringing about a threshold voltage difference of a value of 2*DVT between said nMOS transistors associated with the second pair of said gate stacks,
• at least a first pair of said gate stacks of said pMOS transistors comprise one and the same gate material, and at least a second pair of said gate stacks of said pMOS transistors comprise gate materials having separate work functions, the work function difference between the gate materials of said at least the second pair of said gate stacks bringing about a threshold voltage difference of the value of 2*DVT between said pMOS transistors associated with the second pair of said gate stacks,
• at least one gate stack of one of said nMOS transistors has one and the same gate material as a gate stack of one of said pMOS transistors,
• said nMOS transistors have only two different channel doping configurations, and said pMOS transistors have only two different channel doping configurations, where a difference in channel doping configuration between a pair of nMOS transistors brings about a threshold voltage difference DVT, and a difference in channel doping configuration between a pair of pMOS transistors brings about the threshold voltage difference DVT, and
• the following equation is satisfied:
• Gp*Vdds−Gn*Gnds=Sn*|σn|+Sp*(|σp|−1.65*109)−VarCais+K,
• where Gn is the sensitivity of the threshold voltage of the nMOS transistors to the doping of the first well, Sn is the sensitivity of the threshold voltage of the nMOS transistors to the tensile stress in their channel region, σn is the amplitude of the tensile stress in the channel region of the nMOS transistors, Gp is the sensitivity of the threshold voltage of the pMOS transistors to the doping of the second well, Sp is the sensitivity of the threshold voltage of the pMOS transistors to the compressive stress in their channel region, σp is the amplitude of the tensile stress in the channel region of the pMOS transistors, VarCais is a threshold voltage shift dependent on the doping of the first and second wells, and
• where K=2*DVT if the various gate stacks of said nMOS and pMOS transistors comprise only two different gate material compositions, and K=0 if the various gate stacks of said nMOS and pMOS transistors comprise at least three different gate material compositions.