Method of manufacturing a field effect transistor

A method of manufacturing a field effect transistor semiconductor device comprising the steps of

• (a) forming a substrate of a monocrystalline semiconductor material, said substrate having a surface orientated parallel to a crystallographic plane of said semiconductor material,
• (b) forming a first layer of a first dielectric material at said surface,
• (c) forming at least one first mask on said first layer
• (d) etching said first layer relative to said first mask by reactive ion etching to obtain at least one first dielectric area of said first layer having a shape of said first mask, said first mask being disposed on said first dielectric area,
• (e) forming a second mask at a spacing around said first dielectric area to expose portions of said substrate through a first opening,
• (f) implanting ions into said substrate through said first opening to form source and drain regions of a first conductivity in said substrate, said source and drain regions having a first resistivity different from a resistivity of said substrate,
• (g) removing said second mask,
• (h) forming at least one second layer over each of said first layer, said source and drain regions, and said substrate, said second layer being a second dielectric material with a uniform thickness, said uniform thickness of said second layer being at least equal to a thickness of said first dielectric area,
• (i) planarizing the semiconductor device to said thickness of said first dielectric area to expose said first dielectric area,
• (j) reactive ion etching said first dielectric area down to said substrate to form at least one second opening through said second layer to said substrate,
• (k) implanting ions into said substrate through said second opening to form at least one active layer of said first conductivity, said active layer having a second resistivity different from said source and drain regions,
• (l) forming first spacers in said second opening at edges of said second layer, said first spacers being made of said second dielectric material, and said first spacers reducing dimensions of said second opening to a length L,
• (m) depositing gate metal layer in said at least one second opening to a thickness exceeding said second dielectric material, said gate metal layer extending over said second dielectric material at a uniform thickness, and said gate metal layer having a depression at said second opening,
• (n) depositing a further layer over said gate metal layer to a further uniform thickness, said further layer being selected from the group consisting of titanium (Ti) and said first dielectric material,
• (o) planarizing said semiconductor device down to said gate metal layer, a portion of said further layer remaining in said depression,
• (p) etching said gate metal layer around said portion of said further layer down to said second layer by one of selective reactive ion etching and a beam of ions of a neutral gas, said portion acting as a third mask to form at least one gate electrode having said length L,
• (q) forming second spacers on exposed edges of said gate electrode to form a peripheral dielectric part around said gate electrode at right angles to said second layer, said peripheral dielectric part being of said first dielectric material, and
• (r) etching said second layer down to said surface of said substrate to expose said source and drain regions and said substrate by selective reactive ion etching, said etching being prolonged to laterally etch under said peripheral dielectric part.