H05K 2201/09227
Layout details of a plurality of traces
Official title: Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
H05K2201/09227 (Layout details of a plurality of traces) appears on 726 US grants and 908 published applications in this corpus.
Search patents in H05K- Granted patents
- 726
- Published applications
- 908
- Assignees
- 379
- Inventors
- 1,801
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 2 | 0 |
| 1987 | 0 | 0 |
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 2 | 0 |
| 1991 | 4 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 1 | 0 |
| 1996 | 2 | 0 |
| 1997 | 1 | 0 |
| 1998 | 7 | 0 |
| 1999 | 4 | 0 |
| 2000 | 12 | 0 |
| 2001 | 15 | 7 |
| 2002 | 12 | 11 |
| 2003 | 15 | 13 |
| 2004 | 13 | 16 |
| 2005 | 9 | 15 |
| 2006 | 11 | 24 |
| 2007 | 17 | 17 |
| 2008 | 18 | 31 |
| 2009 | 12 | 19 |
| 2010 | 21 | 22 |
| 2011 | 20 | 14 |
| 2012 | 18 | 11 |
| 2013 | 14 | 21 |
| 2014 | 15 | 36 |
| 2015 | 21 | 31 |
| 2016 | 24 | 29 |
| 2017 | 35 | 28 |
| 2018 | 30 | 58 |
| 2019 | 65 | 50 |
| 2020 | 50 | 62 |
| 2021 | 53 | 60 |
| 2022 | 55 | 39 |
| 2023 | 34 | 63 |
| 2024 | 44 | 35 |
| 2025 | 37 | 54 |
| 2026 | 29 | 142 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Flexible printed circuit to suspension soldering improvement6 Oct 2026US 12,757,332 B2Western Digital Technologies, Inc.
- Method and apparatus for surface mount connections8 Sep 2026US 12,731,922 B2Ciena Corporation
- Stretchable substrate, and method for manufacturing stretchable substrate8 Sep 2026US 12,733,091 B2Korea Photonics Technology Institute
- Jump-fusing and tailored PCB system for loop inductance reduction8 Sep 2026US 12,733,513 B2Texas Instruments Incorporated
- Flexible circuits configured for heat spreading in a wearable display25 Aug 2026US 12,720,667 B2Google Inc.
- Stepped trace design for impedance compensation of high-speed differential pair channels8 Oct 2026US 2026/0313784 A1Advanced Micro Devices, Inc.
- Overlapped interconnect with enhanced design1 Oct 2026US 2026/0304601 A1Micron Technology, Inc.
- Substrate and electronic device24 Sep 2026US 2026/0292970 A1Kioxia Corporation
- Integrated circuit packages having partial pad vertical interconnect access24 Sep 2026US 2026/0292981 A1Intel Corporation
- Integrated circuit packages having ground paired partial pad vertical interconnect access24 Sep 2026US 2026/0293720 A1Intel Corporation
Most cited
By later US patents
- Optimized routing scheme for an integrated circuit/printed circuit board167US 5,847,936 ASun Microsystems, Inc. · 1998
- Mirrored pin assignment for two sided multi-chip layout162US 5,502,621 AHewlett-Packard Company · 1996
- Small outline memory module153US 6,137,709 AIntel Corporation · 2000
- Small outline rambus in-line memory module141US 6,061,263 AIntel Corporation · 2000
- Fine dimension stacked vias for a multiple layer circuit board structure119US 5,699,613 AInternational Business Machines Corporation · 1997