US 5,699,613 A · Fine dimension stacked vias for a multiple layer circuit board structure

Abstract

A method of manufacturing a multiple layer circuit board with stacked vias of fine dimension and pitch. A base laminate with conductive pattern is coated with a dielectric which is photolithographically processed to create holes exposing selected regions of the underlying conductive pattern. The holes through the dielectric are plated to form via connections between the surface and the conductive pattern on the base laminate. The recess created by the via is filled with a conductive and plateable polymer which upon curing forms a conductive plug. A second dielectric layer is deposited on the board structure and in succession photolithographically processed to expose the underlying plated via and plug. The hole in the second dielectric is plated and filled with conductive polymer so as to create a second via vertically aligned with and electrically connected to the underlying first via. The ability to form fine pitch stacked vias is particularly important for printed circuit board structures such as carriers of flip chip die, in that the fine pitch of the solder ball array of the flip chip needs to be expanded and/or disbursed through multiple board layers with minimum area and electrical degradation.

Claims10

Dependent claims

A method of manufacturing a multiple layer circuit board with stacked electrical interconnections, comprising the ordered steps of:

forming holes through a base laminate having a front side and a back side;
forming electrical interconnect patterns on the front and back sides of the base laminate adjacent the holes;
masking the holes from the front side of the base laminate;
filling the holes with a conductive polymer from the back side of the base laminate;
curing the conductive polymer to form conductive plugs through the holes;
forming a first dielectric layer on one of the front or back sides of the base laminate;
selectively removing regions of the first dielectric layer at selected number of the conductive plugs to form vias having openings through the first dielectric layer;
the openings exposing the selected conductive plugs;
plating to form electrical connections through the openings of the vias at the selectively removed regions;
filling recesses produced by plating into the openings of the vias with conductive polymer;
and
curing the conductive polymer to form conductive plugs within the recesses at the filled vias.

9 more elements

A method of manufacturing a multiple layer circuit board with stacked vias, comprising the steps of:

forming a first electric interconnect pattern on the front side of a base laminate with a front side and a back side;
forming a first dielectric layer on the front side of the base laminate;
selectively removing regions of the first dielectric layer to form first vias exposing the electrical interconnect pattern at selected portions through the first dielectric layer;
plating to form electrical connections through the first vias at the selectively removed regions;
filling recesses produced by plating into the first vias with first conductive polymer;
curing the first conductive polymer to form first plugs within the recesses at the first vias;
forming a second dielectric layer on the front side of the base laminate;
selectively removing regions of the second dielectric layer to form second vias exposing selected number of the first plugs through the second dielectric layer;
plating to form electrical connections through the second vias at the selectively removed regions of the second dielectric;
filling recesses produced by plating into the second vias with second conductive polymer;
and
curing the second conductive polymer to form second plugs within the recesses at the second vias, wherein the second plugs are respectively aligned with and electrically connected to the underlying first plugs.

9 more elements

Dependencies are inferred from the claim text.

Fine dimension stacked vias for a multiple layer circuit board structure

Life of this patent

Fine dimension stacked vias for a multiple layer circuit board structure

Life of this patent

Abstract

Claims10