H03K 2005/00195
Using fet's
Official title: {using FET's}
H03K2005/00195 (Using fet's) appears on 456 US grants and 315 published applications in this corpus.
Search patents in H03K- Granted patents
- 456
- Published applications
- 315
- Assignees
- 209
- Inventors
- 847
- Latest grant
- 26 May 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 3 | 0 |
| 1984 | 4 | 0 |
| 1985 | 0 | 0 |
| 1986 | 2 | 0 |
| 1987 | 8 | 0 |
| 1988 | 6 | 0 |
| 1989 | 7 | 0 |
| 1990 | 9 | 0 |
| 1991 | 18 | 0 |
| 1992 | 17 | 0 |
| 1993 | 16 | 0 |
| 1994 | 7 | 0 |
| 1995 | 5 | 0 |
| 1996 | 4 | 0 |
| 1997 | 4 | 0 |
| 1998 | 3 | 0 |
| 1999 | 2 | 0 |
| 2000 | 13 | 0 |
| 2001 | 11 | 1 |
| 2002 | 18 | 15 |
| 2003 | 24 | 30 |
| 2004 | 19 | 11 |
| 2005 | 14 | 19 |
| 2006 | 14 | 16 |
| 2007 | 20 | 15 |
| 2008 | 15 | 27 |
| 2009 | 14 | 20 |
| 2010 | 19 | 16 |
| 2011 | 20 | 12 |
| 2012 | 9 | 5 |
| 2013 | 6 | 5 |
| 2014 | 5 | 6 |
| 2015 | 5 | 6 |
| 2016 | 10 | 11 |
| 2017 | 9 | 15 |
| 2018 | 12 | 8 |
| 2019 | 16 | 17 |
| 2020 | 15 | 11 |
| 2021 | 12 | 10 |
| 2022 | 16 | 13 |
| 2023 | 8 | 7 |
| 2024 | 6 | 5 |
| 2025 | 4 | 4 |
| 2026 | 4 | 10 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- H03K 2005/00208Using differential stagesIndexing code145
- H03K 2005/00202Using current mirrorsIndexing code63
- H03K 2005/00215Where the conduction path of multiple fet's is in parallel or inIndexing code30
- H03K 2005/00221Where the conduction path of the different output fet's is connected inIndexing code27
Recent patents
- Glitch-free delay line architecture26 May 2026US 12,640,718 B1Cadence Design Systems, Inc.
- High-speed delay line for die-to-die interconnect3 Mar 2026US 12,567,858 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Programmable delays and methods thereof24 Feb 2026US 12,562,723 B2Ferroelectric Memory GmbH
- Delay circuit and operational method thereof20 Jan 2026US 12,531,552 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Coherent sampling true random number generation in FD-SOI technology28 Oct 2025US 12,456,968 B2Commissariat A L' Energie Atomique Et Aux Energies Alternatives
- Dynamic duty cycle monitor and correction circuit10 Sep 2026US 2026/0269817 A1Apple Inc.
- Integrated circuit and phase locked loop circuit including the same30 Jul 2026US 2026/0221975 A1Samsung Electronics Co., Ltd.
- Delay Cells with Constant Output Delay16 Jul 2026US 2026/0205101 A1Apple Inc.
- Delay Line Unit Circuits and Methods18 Jun 2026US 2026/0172011 A1Arm Limited
- Duty cycle adjust with independent rising and falling edge control18 Jun 2026US 2026/0172014 A1Micron Technology, Inc.
Most cited
By later US patents
- Delay circuit for gate-array LSI371US 4,700,089 AFujitsu Limited · 1987
- Delay-locked loop circuitry for clock delay adjustment248US 6,125,157 ARambus Inc. · 2000
- Phase-locked loop delay line196US 4,922,141 AWestern Digital Corporation · 1990
- Delay locked loop circuitry for clock delay adjustment169US 6,539,072 B1Rambus Inc. · 2003
- Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle111US 5,317,202 AIntel Corporation · 1994