High-speed delay line for die-to-die interconnect
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShenggao Li
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Abstract
Systems and methods are provided for a delay line circuit that comprises a delay line core and a first current mirror circuit. The delay line core includes a plurality of inverters connected in series. Each of the plurality of inverters is coupled to a first common node. The first current mirror circuit includes a first current source configured to generate a first digital-to-analog (DAC) current, a first transistor coupled to the first current source, and a plurality of first controlling transistors coupled to the first transistor and the first common node. The plurality of first controlling transistors generates a first mirror current at the first common node based on the first DAC current. A delay time of the delay line core is controlled based on the first mirror current.
Claims20
A delay line circuit comprising:
- a delay line core including a plurality of inverters connected in series, each of the plurality of inverters having a first controlling node and a second controlling node;
- a first current mirror circuit including:
- a first current source configured to generate a first digital-to-analog converter (DAC) current;
- a first transistor coupled to the first current source;
- and
- a plurality of first controlling transistors coupled to the first transistor and the first controlling node of a separate inverter within the plurality of inverters;
- and
- a first duty cycle control circuit coupled to alternating inverters within the delay line core and configured to control a delay time of the alternating inverters;
- each of the plurality of first controlling transistors configured to generate a first mirror current at the first controlling node of the separate inverter, the first mirror current based on the first DAC current, a delay time of the separate inverter being controlled based on the first mirror current.
A method of controlling a delay line comprising:
- determining a delay time of a delay line core;
- based on the delay time of the delay line core, connecting or disconnecting a particular number of controlling transistors to a first transistor, the connecting or disconnecting of the particular number of controlling transistors providing a coarse-tuning of a mirror current;
- and
- based on the delay time of the delay line core, adjusting a current output of a digital-to-analog converter (DAC) coupled to the first transistor, the adjustment of the current output providing a fine-tuning of the mirror current;
- and
- based on the mirror current, controlling the delay time and a duty cycle of the delay line core.
A delay line circuit comprising:
- a delay line core including a plurality of inverters connected in series, each of the plurality of inverters having a first controlling node;
- and
- a first current mirror circuit including:
- a first current source configured to generate a first digital-to-analog converter (DAC) current;
- a first transistor coupled to the first current source;
- and
- a plurality of first controlling transistors coupled to the first transistor and the first controlling node of a separate inverter within the plurality of inverters;
- and
- a first duty cycle control circuit coupled to at least one of the inverters within the delay line core and configured to control a delay time of the at least one of the inverters;
- each of the plurality of first controlling transistors configured to generate a first mirror current at the first controlling node of the separate inverter.
Dependencies are inferred from the claim text.