Delay Cells with Constant Output Delay

A method for generating an output voltage signal, comprising:

• configuring a plurality of delay cells in a delay line, each delay cell including inverter circuitry to produce an output voltage signal based on an input voltage signal, each inverter circuitry including a current source, a first transistor coupled to the current source, a second transistor coupled to the first transistor, and a current sink coupled to the second transistor;
• generating a bias signal utilizing a first reference transistor and a second reference transistor, the first transistor matching one or more process parameters and a transistor type of the first reference transistor, the second transistor matching one or more process parameters and a transistor type of the second reference transistor;
• and
• biasing the current source and the current sink based on the bias signal to maintain a constant output delay of the first transistor and the second transistor to produce the output voltage signal based on an input voltage signal.