H03K 2005/0015
Layout of the delay element
Official title: {Layout of the delay element}
H03K2005/0015 (Layout of the delay element) appears on 994 US grants and 720 published applications in this corpus.
Search patents in H03K- Granted patents
- 994
- Published applications
- 720
- Assignees
- 384
- Inventors
- 1,753
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 2 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 2 | 0 |
| 1982 | 1 | 0 |
| 1983 | 3 | 0 |
| 1984 | 8 | 0 |
| 1985 | 1 | 0 |
| 1986 | 4 | 0 |
| 1987 | 24 | 0 |
| 1988 | 13 | 0 |
| 1989 | 23 | 0 |
| 1990 | 13 | 0 |
| 1991 | 29 | 0 |
| 1992 | 26 | 0 |
| 1993 | 25 | 0 |
| 1994 | 11 | 0 |
| 1995 | 6 | 0 |
| 1996 | 7 | 0 |
| 1997 | 7 | 0 |
| 1998 | 4 | 0 |
| 1999 | 4 | 0 |
| 2000 | 20 | 0 |
| 2001 | 25 | 6 |
| 2002 | 25 | 23 |
| 2003 | 35 | 54 |
| 2004 | 38 | 36 |
| 2005 | 40 | 55 |
| 2006 | 43 | 36 |
| 2007 | 42 | 45 |
| 2008 | 42 | 51 |
| 2009 | 42 | 44 |
| 2010 | 40 | 32 |
| 2011 | 38 | 22 |
| 2012 | 22 | 7 |
| 2013 | 13 | 10 |
| 2014 | 23 | 24 |
| 2015 | 20 | 21 |
| 2016 | 25 | 23 |
| 2017 | 23 | 36 |
| 2018 | 27 | 25 |
| 2019 | 43 | 43 |
| 2020 | 37 | 21 |
| 2021 | 36 | 24 |
| 2022 | 27 | 18 |
| 2023 | 20 | 15 |
| 2024 | 10 | 11 |
| 2025 | 14 | 18 |
| 2026 | 10 | 20 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- H03K 2005/00195Using fet'sIndexing code456
- H03K 2005/00234Using circuits having two logic levelsIndexing code363
- H03K 2005/00156Using opamps, comparators, voltage multipliers or other analog building blocksIndexing code150
- H03K 2005/00163Using bipolar transistorsIndexing code64
- H03K 2005/00228Having complementary input and output signalsIndexing code38
- H03K 2005/0028Using varicapsIndexing code16
- H03K 2005/00189In bicmos technologyIndexing code4
Recent patents
- Adaptive clocking architecture25 Aug 2026US 12,719,461 B2Arm Limited
- Signal transporting system and signal transporting method14 Jul 2026US 12,683,589 B2Realtek Semiconductor Corp.
- Combined feedforward and fixed time delay2 Jun 2026US 12,647,014 B2STMicroelectronics International N. V.
- Delay locked loop and semiconductor memory device2 Jun 2026US 12,647,119 B2Winbond Electronics Corp.
- Glitch-free delay line architecture26 May 2026US 12,640,718 B1Cadence Design Systems, Inc.
- Inter-lane skew compensation method24 Sep 2026US 2026/0291479 A1Mediatek Inc.
- Dynamic duty cycle monitor and correction circuit10 Sep 2026US 2026/0269817 A1Apple Inc.
- Control circuit, semiconductor memory device, and control method of semiconductor memory device20 Aug 2026US 2026/0246458 A1Winbond Electronics Corp.
- Integrated circuit and phase locked loop circuit including the same30 Jul 2026US 2026/0221975 A1Samsung Electronics Co., Ltd.
- Filter and Refresh Circuit Architecture for Electrical Isolators23 Jul 2026US 2026/0213740 A1Elevation Microsystems, Inc.
Most cited
By later US patents
- Delay circuit for gate-array LSI371US 4,700,089 AFujitsu Limited · 1987
- Delay-locked loop circuitry for clock delay adjustment248US 6,125,157 ARambus Inc. · 2000
- Phase-locked loop delay line196US 4,922,141 AWestern Digital Corporation · 1990
- Delay locked loop circuitry for clock delay adjustment169US 6,539,072 B1Rambus Inc. · 2003
- Method and apparatus for applying and monitoring programmed test signals during automated testing of electronic circuits131US 4,646,299 AFairchild Semiconductor Corporation · 1987