Adaptive clocking architecture

A device comprising:

• adaptive clocking architecture with a controller and multiple stages of latches and logic gates that are coupled in a delay line,
• wherein each logic gate provides a delayed clock signal based on a reset signal,
• wherein each latch receives the delayed clock signal as a data input and a clock signal as a clock input and provides a sample out signal in the delay line as a latched output based on the clock signal,
• wherein each latch provides a delayed edge in the delay line of a next clock cycle, and
• wherein the controller is configured to stretch a pulse width of the clock signal based on the delayed edge.

A device comprising:

• a clock controller that provides clock signals and reset signals based on an enable signal, an input reset signal and an input clock signal;
• and
• a phase generator that generates output signals and sampling signals based on the clock signals and the reset signals from the clock controller,
• wherein the phase generator includes multiple stages of latches and logic gates coupled in a delay line configuration,
• wherein each latch receives a delayed clock signal as data input and provides a sample out signal as a latched output based on a clock signal, and
• each latch provides a delayed edge of a next clock cycle to enable a state machine to calculate a delayed edge to be used to stretch the pulse width of the clock signal.