Control circuit, semiconductor memory device, and control method of semiconductor memory device

Abstract

A control circuit is provided. The control circuit includes a delay section, a detection section, and a control section. The delay section to which a first signal is input has a plurality of delay units coupled in series. Each of the plurality of delay units delays the first signal input thereto. The detection section detects a number of delay units among the plurality of delay units through which the first signal passes when the second signal is input to the detection section after the first signal is input to the delay section. The second signal is a delay signal of the first signal. The control section is configured to control a transmission path of the first signal in the delay section, which causes the number of delay units through which the first signal passes to be equal to the number of delay units detected by the detection section.

Dependencies are inferred from the claim text.