Delay locked loop and semiconductor memory device
AssigneeWinbond Electronics Corp.
InventorShinya Okuno
Life of this patent
Estimating the term…
Abstract
The present invention provides a delay locked loop (DLL) that can complete the process of adjusting the delay of an internal clock signal within a predetermined execution period. The DLL includes a DLL control circuit and a delay line circuit. The DLL control circuit sets the delay amount based on the phase difference between an input clock signal and an output clock signal. The delay line circuit performs a delay operation on the input clock signal according to the delay amount, thereby generating the output clock signal. The delay line circuit includes a plurality of delay units, each delay unit includes at least one delay element, and one of the delay units includes a greater number of delay elements than another delay unit.
Claims18
A delay locked loop (DLL), comprising:
- a DLL control circuit, configured to set amount of delay according to a phase difference between an input clock signal and an output clock signal;
- a delay line circuit, receiving the input clock signal, and configured to perform a delay operation on the input clock signal according to the amount of delay, thereby generating the output clock signal;
- wherein the delay line circuit includes a plurality of delay units, each of the plurality of delay units includes at least one delay element, and a first number of delay elements in at least one of the delay units is greater than a second number of delay elements in at least another one of the delay units;
- wherein the delay locked loop further includes:
- an input buffer, configured to buffer a received external clock signal to generate the input clock signal;
- a replica circuit, configured to generate a feedback signal according to the output clock signal;
- and
- a phase detection circuit, coupled between the replica circuit and the DLL control circuit, receiving the input clock signal and the feedback signal, and configured to generate a phase signal for indicating the phase difference to the DLL control circuit;
- wherein the DLL control circuit generates a selection control signal and a control signal for indicating the amount of delay according to the phase signal, and the delay line circuit activates the corresponding one of the plurality of delay units according to the selection control signal and the control signal to delay the input clock signal.
Dependencies are inferred from the claim text.