Inter-lane skew compensation method
AssigneeMediatek Inc.
InventorsChih-Lun Chuang, Pin-Yang Huang
Life of this patent
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Abstract
The present invention provides a circuitry including a first sampling circuit and a second sampling circuit. The first sampling circuit is configured to use a first clock signal to sample first data to generate sampled first data to a plurality of first lanes of a transmitter via a plurality of first connection lines. The second sampling circuit is configured to use a second clock signal to sample second data to generate sampled second data to a plurality of second lanes of the transmitter via a plurality of second connection lines. Lengths of the plurality of second connection lines are longer than lengths of the plurality of first connection lines, and delay amount of the second clock signal is less than delay amount of the first clock signal.
Claims7
A circuitry, comprising:
- a first sampling circuit, configured to use a first clock signal to sample first data to generate sampled first data, wherein the first data is received from a plurality of first lanes of a receiver via a plurality of first connection lines;
- and
- a second sampling circuit, configured to use a second clock signal to sample second data to generate sampled second data, wherein the second data is received from a plurality of second lanes of the receiver via a plurality of second connection lines;
- wherein lengths of the plurality of second connection lines are longer than lengths of the plurality of first connection lines, and delay amount of the second clock signal is greater than delay amount of the first clock signal.
Dependencies are inferred from the claim text.