H03K 2005/00013
Delay, i.e. output pulse is delayed after input pulse and pulse length
Official title: {Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse}
H03K2005/00013 (Delay, i.e. output pulse is delayed after input pulse and pulse length) appears on 2,975 US grants and 2,482 published applications in this corpus.
Search patents in H03K- Granted patents
- 2,975
- Published applications
- 2,482
- Assignees
- 759
- Inventors
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- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 2 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 2 | 0 |
| 1982 | 1 | 0 |
| 1983 | 3 | 0 |
| 1984 | 8 | 0 |
| 1985 | 1 | 0 |
| 1986 | 5 | 0 |
| 1987 | 25 | 0 |
| 1988 | 13 | 0 |
| 1989 | 23 | 0 |
| 1990 | 13 | 0 |
| 1991 | 30 | 0 |
| 1992 | 31 | 0 |
| 1993 | 33 | 0 |
| 1994 | 17 | 0 |
| 1995 | 8 | 0 |
| 1996 | 7 | 0 |
| 1997 | 11 | 0 |
| 1998 | 7 | 0 |
| 1999 | 28 | 0 |
| 2000 | 62 | 0 |
| 2001 | 67 | 29 |
| 2002 | 85 | 63 |
| 2003 | 79 | 106 |
| 2004 | 67 | 93 |
| 2005 | 95 | 112 |
| 2006 | 120 | 107 |
| 2007 | 107 | 103 |
| 2008 | 96 | 129 |
| 2009 | 98 | 122 |
| 2010 | 116 | 102 |
| 2011 | 123 | 77 |
| 2012 | 82 | 37 |
| 2013 | 54 | 51 |
| 2014 | 72 | 67 |
| 2015 | 56 | 66 |
| 2016 | 103 | 107 |
| 2017 | 132 | 117 |
| 2018 | 112 | 123 |
| 2019 | 162 | 135 |
| 2020 | 154 | 108 |
| 2021 | 129 | 118 |
| 2022 | 139 | 116 |
| 2023 | 122 | 103 |
| 2024 | 90 | 114 |
| 2025 | 100 | 104 |
| 2026 | 84 | 73 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Transmitter interpolating clock signal, communication device including the same, and method of operating the same6 Oct 2026US 12,756,382 B2Samsung Electronics Co., Ltd.
- Systems and methods for clock generation and calibration in photonic systems29 Sep 2026US 12,750,045 B2Avago Technologies International Sales Pte. Limited
- Delay line calibration method22 Sep 2026US 12,743,056 B2Magics Technologies
- Adjustable power FET driver22 Sep 2026US 12,744,526 B2Texas Instruments Incorporated
- Phase interpolation circuit8 Sep 2026US 12,732,173 B2Thine Electronics, Inc.
- Communication circuits including a differential to quadrature phase generator8 Oct 2026US 2026/0312785 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Digital sensor for detecting electromagnetic fault injection1 Oct 2026US 2026/0298994 A1Mediatek Inc.
- Gate driver circuit1 Oct 2026US 2026/0302922 A1Renesas Design (UK) Limited
- Positive/negative skew calibration in active electrical cables1 Oct 2026US 2026/0303076 A1Marvell Asia Pte Ltd
- Data acquisition system24 Sep 2026US 2026/0291473 A1Cirrus Logic International Semiconductor Ltd.
Most cited
By later US patents
- Scannable sense amplifier circuit421US 5,915,084 AAdvanced Micro Devices, Inc. · 1999
- Delay circuit for gate-array LSI371US 4,700,089 AFujitsu Limited · 1987
- Delay-locked loop circuitry for clock delay adjustment248US 6,125,157 ARambus Inc. · 2000
- Method and apparatus for receiving high speed signals with low latency243US 6,396,329 B1Rambus Inc. · 2002
- Phase-locked loop delay line196US 4,922,141 AWestern Digital Corporation · 1990