Delay line calibration method

A time-to-digital (TDC) device for measuring a time lapse between a trigger and a pulse of a clock, comprising a clock, a delay line, a delay line inject block, a register and a processing unit, wherein

• the delay line inject block comprises a trigger input for receiving a trigger, and a clock input operably connected to the clock for receiving clock pulses;
• the delay line inject block comprises a delay line output operably connected to the delay line for providing a delay line signal to the delay line, and a sampling output operably connected to the register for indicating when a delay line state is to be obtained;
• the delay line comprises a chain of delay cells, each delay cell configured for delaying the propagation of a delay line signal through said chain;
• the register is operably connected to each of the delay cells of the delay line, the register being configured to obtain a delay line state upon receiving a sampling signal from the delay line inject block, the delay line state representing the state of each delay cell, and the register further being configured to provide the processing unit with the delay line state, and
• the processing unit is configured to receive a delay line state from the register, wherein the delay line inject block is configured to:
• upon receiving a trigger at the trigger input:
• provide a delay line signal to the delay line via the delay line output, said delay line signal based on said trigger received at the trigger input,
• subsequently, at a measurement clock pulse received at the clock input:
• provide a sampling signal at the sampling output, whereupon the register is configured to obtain a measurement delay line state and provide the measurement delay line state to the processing unit,
• subsequently and within half a clock period of said measurement clock pulse:
• base the delay line signal on a clock signal received at the clock input, and provide said delay line signal based on the clock signal to the delay line,
• subsequently, at a calibration clock pulse:
• provide a sampling signal at the sampling output, whereupon the register is configured to obtain a calibration delay line state and provide the calibration delay line state to the processing unit, and
• wherein the processing unit is configured to compute the time lapse between the trigger and the measurement clock pulse based on the measurement delay line state and the calibration delay line state.