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US 12,732,173 B2Granted
Phase interpolation circuit
AssigneeThine Electronics, Inc.
InventorsTomohiro Ishida, Shunichi Kubo
Life of this patent
Estimating the term…
Abstract
A current control unit 10 of a phase interpolation circuit 1 includes M slice circuits 60B0 to 60BM-1 having a common configuration. Each slice circuit 60Bm includes a selector 61, a PMOS transistor 62, an NMOS transistor 63, a PMOS transistor 64, an NMOS transistor 65, a first standby voltage set circuit 70, and a second standby voltage set circuit 80. The first standby voltage set circuit 70 has a configuration connecting the first node N1 and the voltage source via a switch the on/off of which is set according to the output signal from the selector 61, and sets the first node N1 to a standby voltage by supplementarily charging and discharging the parasitic capacitance of the first node N1 when the switch is in the on state.
Claims10
A phase interpolation circuit, comprising:
- a scalable INV-type phase interpolation circuit configured to include a current control unit including a plurality of slice circuits, the plurality of slice circuits outputting, from an output terminal, a current signal corresponding to any signal selected from a plurality of input signals having phases different from each other, and output a signal a phase of which is interpolated on a basis of the plurality of input signals,
- wherein each of the slice circuits includes:
- a selector configured to select and output any signal of the plurality of input signals on a basis of a selection signal;
- a first PMOS transistor having a gate to which the signal output from the selector is input, a source connected to a high potential supply terminal, and a drain;
- an first NMOS transistor having a gate to which the signal output from the selector is input, a source connected to a low potential supply terminal, and a drain;
- a first current source provided between the drain of the first PMOS transistor and the output terminal;
- a second current source provided between the drain of the first NMOS transistor and the output terminal;
- a first standby voltage set circuit configured to set a first node between the drain of the first PMOS transistor and the first current source to a standby voltage by charging and discharging a parasitic capacitance at the first node, wherein the first standby voltage set circuit has a first switch that receives the signal output from the selector to connect a first potential to the first node;
- and
- a second standby voltage set circuit configured to set a second node between the drain of the first NMOS transistor and the second current source to a standby voltage by charging and discharging a parasitic capacitance at the second node, wherein the second standby voltage set circuit has a second switch that receives the signal output from the selector to connect a second potential to the second node.
7 more elements
A phase interpolation circuit, comprising:
- a scalable INV-type phase interpolation circuit configured to include a current control unit including a plurality of slice circuits, the plurality of slice circuits outputting, from an output terminal, a current signal corresponding to any signal selected from a plurality of input signals having phases different from each other, and output a signal a phase of which is interpolated on a basis of the plurality of input signals,
- wherein each of the slice circuits includes:
- a selector configured to select and output any signal of the plurality of input signals on a basis of a selection signal;
- a PMOS transistor having a gate to which the signal output from the selector is input, a drain connected to the output terminal, and a source;
- an NMOS transistor having a gate to which the signal output from the selector is input, a drain connected to the output terminal, and a source;
- a first current source provided between the source of the PMOS transistor and a high potential supply terminal;
- a second current source provided between the source of the NMOS transistor and a low potential supply terminal;
- a first standby voltage set circuit configured to set a first node between the source of the PMOS transistor and the first current source to a standby voltage by charging and discharging a parasitic capacitance at the first node, wherein the first standby voltage set circuit has a first switch that receives the signal output from the selector to connect a first potential to the first node;
- and
- a second standby voltage set circuit configured to set a second node between the source of the NMOS transistor and the second current source to a standby voltage by charging and discharging a parasitic capacitance at the second node, wherein the second standby voltage set circuit has a second switch that receives the signal output from the selector to connect a second potential to the second node.
7 more elements
A phase interpolation circuit, comprising:
- a scalable INV-type phase interpolation circuit configured to include a current control unit including a plurality of slice circuits, the plurality of slice circuits outputting, from an output terminal, a current signal corresponding to any signal selected from a plurality of input signals having phases different from each other, and output a signal a phase of which is interpolated on a basis of the plurality of input signals,
- wherein each of the slice circuits includes:
- a selector configured to select and output any signal of the plurality of input signals on a basis of a selection signal;
- a PMOS transistor having a gate to which the signal output from the selector is input, a source connected to a high potential supply terminal, and a drain;
- an NMOS transistor having a gate to which the signal output from the selector is input, a source connected to a low potential supply terminal, and a drain;
- a first current source provided between the drain of the PMOS transistor and the output terminal;
- a second current source provided between the drain of the NMOS transistor and the output terminal;
- a first standby voltage set circuit configured to set a first node between the drain of the PMOS transistor and the first current source to a standby voltage by charging and discharging a parasitic capacitance at the first node;
- and
- a second standby voltage set circuit configured to set a second node between the drain of the NMOS transistor and the second current source to a standby voltage by charging and discharging a parasitic capacitance at the second node,
- wherein the first standby voltage set circuit includes:
- a first voltage follower amplifier configured to receive a potential of the output terminal of the slice circuit;
- and
- an NMOS transistor provided between an output terminal of the first voltage follower amplifier and the first node, the NMOS transistor having a gate to which the signal output from the selector is input, and
- wherein the second standby voltage set circuit includes:
- a second voltage follower amplifier configured to receive a potential of the output terminal of the slice circuit;
- and
- a PMOS transistor provided between an output terminal of the second voltage follower amplifier and the second node, the PMOS transistor having a gate to which the signal output from the selector is input.
15 more elements
A phase interpolation circuit, comprising:
- a scalable INV-type phase interpolation circuit configured to include a current control unit including a plurality of slice circuits, the plurality of slice circuits outputting, from an output terminal, a current signal corresponding to any signal selected from a plurality of input signals having phases different from each other, and output a signal obtained by interpolating a phase on a basis of the plurality of input signals,
- wherein each of the slice circuits includes:
- a selector configured to select and output any signal of the plurality of input signals on a basis of a selection signal;
- a PMOS transistor having a gate to which the signal output from the selector is input, a source connected to a high potential supply terminal, and a drain;
- an NMOS transistor having a gate to which the signal output from the selector is input, a source connected to a low potential supply terminal, and a drain;
- a first current source provided between the drain of the PMOS transistor and the output terminal;
- and
- a second current source provided between the drain of the NMOS transistor and the output terminal,
- the drain of the PMOS transistor and the drain of the NMOS transistor being directly connected to each other.
6 more elements
Dependencies are inferred from the claim text.