Back to results
US 4,700,089 AGranted
Delay circuit for gate-array LSI
AssigneeFujitsu Limited
InventorsShigeru Fujii, Masanori Oozeki
Life of this patent
Estimating the term…
Abstract
A delay circuit for a gate-array LSI including at least one inverter having a plurality of P-channel transistors (Q.sub.1p to Q.sub.4p) and a plurality of N-channel transistors (Q.sub.1n to Q.sub.4n) connected in series. The P-channel/N-channel transistors are driven by an input potential (IN), and the common output of the innermost pair of P-channel/N-channel transistors generates an output.
Claims6
A delay circuit comprising:
- an input terminal (IN);
- an intermediate terminal (C);
- an output terminal (OUT);
- first and second power supply means (V.sub.cc, GND);
- a first inverter (INVA) connected between said input terminal and said intermediate terminal, said first inverter comprising:
- a plurality of first P-channel transistors (Q.sub.1p to Q.sub.4p) connected in series between said first power supply means and said intermediate terminal, said first P-channel transistors being driven by the potential at said input terminal;
- a plurality of first N-channel transistors (Q.sub.1n to Q.sub.4n) connected in series between said intermediate terminal and said second power supply terminal, said first N-channel transistors being driven by the potential at said input terminal;
- and
- a second inverter (INVB) connected between said intermediate terminal and said output terminal, said second inverter comprising:
- a plurality of second P-channel transistors to (Q.sub.1p ' to Q.sub.4p ') connected in series between said first power supply means and said output terminal, said second P-channel transistors being driven by the potential at said intermediate terminal, and
- a plurality of second N-channel transistors (Q.sub.1n ' to Q.sub.4n ') connected in series between said output terminal and said second power supply terminal, said second N-channel transistors being driven by the potential at said intermediate terminal.
8 more elements
A delay circuit comprising:
- an input terminal (IN);
- an output terminal (OUT);
- first and second power supply means (V.sub.cc, GND);
- and
- first and second inverters (INVA, INVB) connected in series between said input terminal and said output terminal, each of said first and second inverters having the same number of P-channel transistors and N-channel transistors connected in series between said first and second power supply terminals;
- the common outputs of some of the pairs of P-channel/N-channel transistors of said second inverter being fed back to the inputs of the pairs of P-channel/N-channel transistors of said first inverter.
3 more elements
A delay circuit comprising:
- an input terminal (IN);
- an output terminal (OUT);
- first and second power supply means (V.sub.cc, GND);
- and
- first and second inverters (INVA, INVB) each having the same number of P-channel transistors and N-channel transistors connected in series between said first and second power supply means;
- the outermost pair of P-channel/N-channel transistors of said first inverter being driven by the potential at said input terminal;
- the pairs of P-channel/N-channel transistors of said second inverter being sequentially driven from the outside to the inside by each common output of the pairs of P-channel/N-channel transistors of said first inverter;
- the pairs of P-channel/N-channel transistors of said first inverter, except for the outermost pair, being sequentially driven by each common output of the pairs of P-channel/N-channel transistors of said second inverter;
- the common output of the innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.
6 more elements
A delay circuit comprising:
- an input terminal (IN);
- an output terminal (OUT);
- first and second power supply means (V.sub.cc, GND);
- and
- first and second inverters (INVA, INVB) each having the same number of P-channel transistors and N-channel transistors connected in series between said first and second power supply means;
- the outermost pair of P-channel/N-channel transistors of said first inverter being driven by the potential at said input terminal;
- the outermost pair of P-channel/N-channel transistors of said second inverter being driven by the common output of the outermost pair of P-channel/N-channel transistors of said first inverter;
- the inside pairs of P-channel/N-channel transistors of said first inverter being driven by the common output of the outermost pair of P-channel/N-channel transistors of said second inverter;
- the inside pairs of P-channel/N-channel transistors of said second inverter being driven by the common output of the innermost pair of P-channel/N-channel transistors of said first inverter;
- the output of the innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.
7 more elements
A delay circuit comprising:
- an input terminal (IN);
- an output terminal (OUT);
- first and second power supply means (V.sub.cc, GND);
- and
- first and second inverters (INVA, INVB) each having the same number of P-channel transistors and N-channel transistors connected in series between said first and second power supply means;
- the outermost pair of P-channel/N-channel transistors of said first inverter being driven by the potential at said input terminal;
- the outermost pair of P-channel/N-channel transistors of said second inverter being driven by the common output of the outermost pair of P-channel/N-channel transistors of said first inverter;
- the inside pairs of P-channel/N-channel transistors of said first inverter being driven by the common output of the innermost pair of P-channel/N-channel transistors of said second inverter;
- the inside pairs of P-channel/N-channel transistors of said second inverter being driven by the common output of the innermost pair of P-channel/N-channel transistors of said first inverter;
- the output of the innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.
7 more elements
Dependencies are inferred from the claim text.