Delay-locked loop circuitry for clock delay adjustment

Circuitry for generating an output clock having a predetermined phase relationship with an input clock, the circuitry comprising:

• selection circuitry having as inputs a set of phase vectors and a selection control signal, each vector separated in time from an adjacent vector by a unit delay, the selection circuitry for selecting a pair of adjacent phase vectors from the set;
• a phase interpolator circuit receiving the selected pair of adjacent phase vectors and a phase adjust signal and generating the output clock, the phase interpolator for adjusting the phase of the output clock;
• at least one feedback delay element coupled to the output clock to produce a feedback clock, the feedback delay element delaying the feedback clock from the output clock by an amount equal to a multiple of the unit delay;
• and
• a phase adjusting circuit receiving the input clock and the feedback clock, wherein the phase adjusting circuit produces the selection control signal for adjusting the selection of a pair of adjacent phase vectors produced by the selection circuitry so that the phase of the input clock lies between the selected pair of adjacent phase vectors and wherein the phase adjusting circuit produces the phase adjust signal for adjusting the phase interpolator so that the feedback clock is in phase with the input clock, wherein the output clock has the predetermined phase relationship with the input clock when the feedback clock is in phase with the input clock, the predetermined phase relationship being a multiple of the unit delay.

Circuitry for generating an output clock signal having a predetermined phase relationship with an input clock signal, the circuitry comprising:

• selection circuitry having as inputs a set of phase vector signals and a selection control signal, each phase vector signal separated in time from an adjacent phase vector signal by a unit delay, the selection circuitry for selecting a pair of adjacent phase vector signals from the set;
• a phase interpolator circuit receiving the selected pair of adjacent phase vector signals and a phase adjust signal and generating a phase interpolator output clock signal, the phase interpolator circuit adjusting the phase of the phase interpolator output clock;
• at least one output delay element to receive the phase interpolator output clock signal and to produce the output clock signal, the output delay element delaying the phase interpolator output clock signal by an amount equal to a multiple of the unit delay;
• and
• a phase adjusting circuit receiving the input clock signal and the phase interpolator output clock signal, wherein the phase adjusting circuit produces the selection control signal for adjusting the selection of a pair of adjacent phase vector signals produced by the selection circuitry so that the phase of the input clock signal lies between the selected pair of adjacent phase vector signals and wherein the phase adjusting circuit produces the phase adjust signal for adjusting the phase interpolator so that the phase interpolator output clock signal is in phase with the input clock signal, wherein the output clock signal has the predetermined phase relationship with the input clock signal when the phase interpolator output clock signal is in phase with the input clock signal, the predetermined phase relationship being a multiple of the unit delay.