Data acquisition system

A data acquisition system comprising:

• sampling circuitry configured to output data samples;
• write clock generator circuitry configured to generate a write clock signal having a predefined frequency;
• read clock generator circuitry;
• spread spectrum modulator circuitry configured to modulate a frequency of the read clock signal to generate a spread spectrum modulated read clock signal, wherein a mean frequency of the spread spectrum modulated read clock signal is equal to the predefined frequency of the write clock signal;
• a first-in first-out memory (FIFO) configured such that data samples can be written to the FIFO in synchronisation with the write clock signal and data samples can be read from the FIFO in synchronisation with the read clock signal;
• and
• control circuitry,
• wherein the control circuitry is configured to trigger data acquisition by the data acquisition system responsive to detection of a transition in the frequency of the spread spectrum modulated read clock signal from the mean frequency.

A data acquisition system comprising:

• sampling circuitry configured to output data samples;
• write clock generator circuitry configured to generate a write clock signal having a predefined frequency;
• read clock generator circuitry;
• spread spectrum modulator circuitry operable to modulate a frequency of the read clock signal to generate a spread spectrum modulated read clock signal, wherein a mean frequency of the spread spectrum modulated read clock signal is equal to the predefined frequency of the write clock signal;
• a first-in first-out memory (FIFO) configured such that data samples can be written to the FIFO in synchronisation with the write clock signal and data samples can be read from the FIFO in synchronisation with the read clock signal;
• and
• control circuitry,
• wherein the control circuitry is configured to trigger operation of the spread spectrum modulator responsive to receiving a signal indicating that data acquisition is to commence.

A data acquisition system comprising:

• sampling circuitry configured to sample an input signal to generate output data samples;
• an asynchronous first-in first-out memory (FIFO) for receiving data samples from the sampling circuitry;
• and
• control circuitry,
• wherein the control circuitry is configured to, responsive to receiving a signal indicating that data acquisition is to commence, delay generation of output data samples by the sampling circuitry until the FIFO can receive the output data samples without risk of FIFO overrun or FIFO underrun.