H03K 2005/00234
Using circuits having two logic levels
Official title: {using circuits having two logic levels}
H03K2005/00234 (Using circuits having two logic levels) appears on 363 US grants and 280 published applications in this corpus.
Search patents in H03K- Granted patents
- 363
- Published applications
- 280
- Assignees
- 190
- Inventors
- 662
- Latest grant
- 14 Jul 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 3 | 0 |
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 12 | 0 |
| 1988 | 6 | 0 |
| 1989 | 9 | 0 |
| 1990 | 1 | 0 |
| 1991 | 6 | 0 |
| 1992 | 2 | 0 |
| 1993 | 6 | 0 |
| 1994 | 1 | 0 |
| 1995 | 0 | 0 |
| 1996 | 3 | 0 |
| 1997 | 1 | 0 |
| 1998 | 1 | 0 |
| 1999 | 1 | 0 |
| 2000 | 2 | 0 |
| 2001 | 7 | 5 |
| 2002 | 6 | 7 |
| 2003 | 13 | 22 |
| 2004 | 13 | 12 |
| 2005 | 16 | 13 |
| 2006 | 12 | 13 |
| 2007 | 13 | 19 |
| 2008 | 17 | 23 |
| 2009 | 21 | 18 |
| 2010 | 14 | 11 |
| 2011 | 17 | 7 |
| 2012 | 11 | 0 |
| 2013 | 4 | 3 |
| 2014 | 10 | 11 |
| 2015 | 9 | 11 |
| 2016 | 13 | 10 |
| 2017 | 12 | 16 |
| 2018 | 13 | 11 |
| 2019 | 22 | 22 |
| 2020 | 16 | 5 |
| 2021 | 16 | 10 |
| 2022 | 10 | 4 |
| 2023 | 11 | 6 |
| 2024 | 2 | 5 |
| 2025 | 7 | 7 |
| 2026 | 1 | 9 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- H03K 2005/00247Using countersIndexing code119
- H03K 2005/00241Using shift registersIndexing code71
- H03K 2005/00267Using d/a or a/d convertersIndexing code25
- H03K 2005/0026Using memories or fifo'sIndexing code24
- H03K 2005/00254Using microprocessorsIndexing code19
- H03K 2005/00273Using digital comparatorsIndexing code16
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- Multi-mode sensor, system-on-chip comprising the same and multi-mode sensing method thereof18 Jun 2026US 2026/0172012 A1Samsung Electronics Co., Ltd.
- Systems and methods for a time domain voltage reference with zero quiescent current consumption14 May 2026US 2026/0135547 A1STMicroelectronics International N. V.
- Methods and apparatus to implement delay lines and analog to digital converters30 Apr 2026US 2026/0121624 A1
Most cited
By later US patents
- Method and apparatus for applying and monitoring programmed test signals during automated testing of electronic circuits131US 4,646,299 AFairchild Semiconductor Corporation · 1987
- Method and apparatus for monitoring automated testing of electronic circuits103US 4,637,020 AFairchild Semiconductor Corporation · 1987
- Divide-by-N differential phase interpolator77US 6,597,212 B1Neoaxiom Corporation · 2003
- Delay control circuit58US 4,845,390 ALSI Logic Corporation · 1989
- Voltage controlled oscillator delay cell and method58US 7,400,183 B1Cypress Semiconductor Corporation · 2008