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US 6,597,212 B1Granted
Divide-by-N differential phase interpolator
AssigneeNeoaxiom Corporation
InventorsDavid Y. Wang, Yu-Chi Cheng
Life of this patent
Estimating the term…
Abstract
A phase interpolator circuit that produces 2m phase resolution elements using a control signal that has less than m bits. The circuit combines the function of a divide-by-N circuit with a phase interpolation circuit enabled by the use of a higher-speed clock as an input. By performing phase interpolation at a high speed and then slowing down the speed for the subsequent circuits, the phase resolution increases and fewer control bits are required.
Claims16
A phase interpolator comprising:
- a plurality of differential latches cross-coupled together to form a divide-by-N circuit having first and second differential input lines with differential input signals of identical frequency but different phases, an differential output line and an interpolation control input line, wherein the differential output from the latches provides an output signal on the output line whose phase is a weighted average of the two different phases of the two input signals on first and second differential input lines, and whose frequency is slower than that of the input signals by a divisional factor of N;
- the interpolation control input line feeding the divide-by-N circuit with a pre-selected weighting ratio affecting the weight given to each of the two input phases of the two input signals for determining said weighted average.
A phase interpolator comprising:
- a plurality of latch circuits connected in series, including a first latch circuit and a last latch circuit connected in a cross-coupled manner, each of the latch circuits having a pair of differential inputs including a positive input and a negative input, and a pair of differential outputs including a positive output and a negative output, the positive output of the first latch circuit being connected to the positive input of a next latch circuit and the negative output of the first latch circuit being connected to the negative input of the next latch circuit, the positive output of the last latch circuit being connected to the negative input of the first latch circuit and the negative output of the last latch circuit being connected to the positive input of the first latch circuit;
- and
- a first differential clock input and a second differential clock input line feeding each latch circuit;
- a interpolation control input line feeding into every latch circuit with a pre-selected weighting ratio affecting the weight given to each of the differential clock input signal.
1 more element
A phase interpolator comprising:
- means for receiving a plurality of clock signals, including a positive clock signal line and a negative clock signal line;
- a plurality of latch circuits connected in series, including a first latch circuit and a last latch circuit that are connected in a cross-coupled manner, and a plurality of intermediate latch circuits connected between the first latch circuit and the last circuit, each latch circuit including a positive differential clock input line and a negative differential clock input line, each latch circuit being assigned a placement number starting with zero for the first latch circuit and increasing in a consecutive manner until the last latch circuit, wherein each latch circuit having an even placement number has the positive and negative differential clock inputs coupled to receive the negative and positive clock signals respectively, wherein each latch circuit having an odd placement number has the positive and negative differential clock inputs coupled to receive the positive and negative clock signals respectively, and
- wherein each of the latch circuits includes a plurality of cross-coupled differential transistor pairs for latching an incoming differential signal, a phase selection means for selecting two adjacent phase signals and a current steering means for distributing current between two of the cross-coupled differential transistor pairs.
Dependencies are inferred from the claim text.