US 12,445,119 B2Granted

Tuning of data interface timing between clock domains

AssigneeTexas Instruments Incorporated

InventorEeshan Miglani

Life of this patent

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Abstract

Analog-to-digital converter (ADC) circuitry including a delay domain ADC that outputs converted analog input data along with a delay domain clock. A clock delay driver outputs a digital domain clock, an early clock leading the digital domain clock signal, and a late clock lagging the digital domain clock. An output latch latches the ADC output by the digital domain clock signal. The circuitry includes a timing error detection circuit with inputs receiving the delay domain clock, the early clock, and the late clock. The timing error detection circuit outputs early and late fail flags responsive to detecting timing errors of the digital domain clock relative to the early and late clocks, respectively. Timing loop circuitry has an input coupled to the error flag output of the timing error detection circuitry, and an output coupled to a control input of the clock delay driver.

Claims20

Dependent claims

A circuit comprising:

a clock delay driver having a clock input receiving an input clock signal, a first output presenting an output domain clock signal having a selected delay relative to the input clock signal, a second output presenting an early clock signal leading the output domain clock signal by a selected interval, and a third output presenting a late clock signal lagging the output domain clock signal by a selected interval;
a latch having a data input, a clock input coupled to the first output of the clock delay driver, and a data output;
a timing error detection circuit having a first input receiving an input domain clock signal, a second input coupled to the second output of the clock delay driver, a third input coupled to the third output of the clock delay driver, and an error flag output presenting early and late fail flags responsive to detecting timing errors of the early and late clock signals, respectively, relative to the input domain clock signal;
and
timing loop circuitry having an input coupled to the error flag output of the timing error detection circuit, and an output coupled to a control input of the clock delay driver.

2 more elements

Analog-to-digital converter (ADC) circuitry, comprising:

a delay domain ADC having an input coupled to receive an input voltage, a data output, and a delay domain clock output;
a clock delay driver having an input receiving an input clock signal, a first output presenting a digital domain clock signal having a selected delay relative to the input clock signal, a second output presenting an early clock signal leading the digital domain clock signal by a selected interval, and a third output presenting a late clock signal lagging the digital domain clock signal by a selected interval;
a timing error detection circuit having a first input coupled to the delay domain clock output of the delay domain ADC, a second input coupled to the second output of the clock delay driver, a third input coupled to the third output of the clock delay driver, the timing error detection circuit configured to present an early fail flag signal responsive to one of a skipped cycle or a double cycle of the early clock signal in a cycle of the delay domain clock signal, and to present a late fail flag signal responsive to one of a skipped cycle or a double cycle of the late clock signal in a cycle of the delay domain clock signal;
and
timing loop circuitry having an input coupled to an error flag output of the timing error detection circuit, and configured to output a delay adjustment to a control input of the clock delay driver responsive to the early fail flag signal and the late fail flag signal.

2 more elements

A method, comprising:

generating a first clock signal at a selected delay from an input clock signal;
generating an early clock signal that leads the first clock signal by a selected interval;
generating a late clock signal that lags the first clock signal by a selected interval;
latching a digital word synchronous with the first clock signal;
generating an early fail flag signal responsive to a skipped or doubled cycle of the early clock signal within a cycle of a second clock signal;
generating a late fail flag signal responsive to a skipped or doubled cycle of the late clock signal within a cycle of the second clock signal;
responsive to the early fail flag signal, increasing the delay of the first clock signal from the input clock signal;
and
responsive to the late fail flag signal, reducing the delay of the first clock signal from the input clock signal.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/524,925Filed 30 Nov 2023
Published: US 2025/0183882 A15 Jun 2025
Granted: 14 Oct 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H03K 5/14
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: by the use of delay lines
H03K 3/356043
The input circuit having a differential configuration: with synchronous operation
H03K 5/135
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: by the use of time reference…
H03K 5/15093
With parallel driven output stages; with synchronously driven series connected output stages: using devices arranged in a shift register