Clock phase converter and phase converting method
AssigneeLx Semicon Co., Ltd.
InventorsJong Suk Lee, Seok Jae Oh
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Abstract
Disclosed are a clock phase converter and a phase converting method that can generate a converted clock signal with a desired amount of delay by selecting and outputting an output signal corresponding to a preset value among output signals of a plurality of delayed clock signal generators that detect the transition of a clock signal and generate delayed clock signals by sequentially delaying the clock signal by a certain period of time.
Claims13
A clock phase converter comprising:
- a delayed clock signal generation unit configured to generate a plurality of delayed clock signals by converting a phase of a clock signal or the phase and a frequency of the clock signal;
- a delayed clock signal storage unit configured to receive, store, and output the clock signal in response to a corresponding delayed clock signal among the plurality of delayed clock signals;
- a delayed clock signal first logic combination unit configured to generate a plurality of exclusive OR signals by performing EXclusive ORing on a logic high signal and a plurality of storage clock signals stored in the delayed clock signal storage unit;
- an encoder configured to generate an encoding output signal by counting logic states of the plurality of exclusive OR signals;
- a divider configured to output, as a selection signal, a value obtained by dividing a preset divide value by the encoding output signal;
- and
- a multiplexer configured to output a selected delayed clock signal, selected in response to the selection signal, among the plurality of delayed clock signals.
A phase converting method performed by a clock phase converter including a delayed clock signal generation unit that is configured to generate a plurality of delayed clock signals by converting a phase of a clock signal or the phase and a frequency of the clock signal, the phase converting method comprising:
- a step of detecting an edge of the clock signal;
- a step of generating the plurality of delayed clock signals sequentially delayed by using a preset delay time;
- a step of encoding the number of states selected from states of the plurality of delayed clock signals;
- a step of generating, as a selection signal, a value (quotient) obtained by dividing an encoded value by a preset divide value;
- and
- a step of selecting and outputting a delayed clock signal corresponding to the selection signal among the plurality of delayed clock signals.
A phase converting method performed by a clock phase converter including a delayed clock signal generation unit that is configured to generate a plurality of delayed clock signals by converting a phase of a clock signal or the phase and a frequency of the clock signal, and being able to convert a phase and a frequency of a delayed clock signal generated, the phase converting method comprising:
- a step of selecting a path;
- a step of generating a plurality of A-path delayed clock signals sequentially delayed by using a preset delay time in correspondence to 0° to 180° of the clock signal CLK when a path A is selected in the step of selecting a path;
- a step of generating a plurality of B-path delayed clock signals sequentially delayed by using a preset delay time in correspondence to 180° to 360° of the clock signal CLK when a path B is selected in the step of selecting a path;
- a step of encoding the number of states selected from states of the plurality of A-path delayed clock signals and the plurality of B-path delayed clock signals;
- a step of generating, as a selection signal, a value (quotient) obtained by dividing an encoded value by a preset divide value;
- and
- a step of selecting and outputting a delayed clock signal corresponding to the selection signal among the plurality of A-path delayed clock signals and the plurality of B-path delayed clock signals.
Dependencies are inferred from the claim text.