Delay control circuit and method, and semiconductor memory

A delay control method, applied to a delay control circuit, comprising:

• receiving a temperature adjustment signal by a clock circuit, and generating a first clock signal according to the temperature adjustment signal, wherein a clock cycle of the first clock signal is a preset value;
• and
• receiving the first clock signal and an initial command signal by a delay circuit, and performing delay processing on the initial command signal according to the first clock signal, so as to obtain a target command signal, wherein a time interval between the target command signal and the initial command signal meets a preset timing condition;
• providing a fuse signal for the oscillator circuit by the fuse circuit, wherein a target mode value indicated by the fuse signal is determined under a test mode;
• and
• generating the first clock signal according to the fuse signal and the temperature adjustment signal by the oscillator circuit;
• setting a value of a second test mode signal to be a first candidate mode value under the test mode by the fuse circuit, and sending the second test mode signal to the oscillator circuit;
• generating a test clock signal according to the second test mode signal by the oscillator circuit;
• and
• receiving a first test mode signal, and selecting the test clock signal for output according to the first test mode signal by the selection circuit.

A semiconductor memory, comprising

• a delay control circuit, wherein the delay control circuit comprises a clock circuit and a delay circuit, wherein
• the clock circuit is configured to receive a temperature adjustment signal, and generate a first clock signal according to the temperature adjustment signal, wherein a clock cycle of the first clock signal is a preset value;
• and
• the delay circuit is configured to receive the first clock signal and an initial command signal, and perform delay processing on the initial command signal according to the first clock signal, so as to obtain a target command signal, wherein a time interval between the target command signal and the initial command signal meets a preset timing condition;
• the clock circuit comprises an oscillator circuit and a fuse circuit, the fuse circuit is configured to provide a fuse signal for the oscillator circuit, wherein a target mode value indicated by the fuse signal is determined under a test mode;
• and
• the oscillator circuit is further configured to generate the first clock signal according to the fuse signal and the temperature adjustment signal;
• the clock circuit further comprises a selection circuit;
• the fuse circuit is further configured to set a value of a second test mode signal to be a first candidate mode value under the test mode, and send the second test mode signal to the oscillator circuit;
• the oscillator circuit is further configured to generate a test clock signal according to the second test mode signal;
• and
• the selection circuit is configured to receive a first test mode signal, and select the test clock signal for output according to the first test mode signal.