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US 4,637,020 AGranted
Method and apparatus for monitoring automated testing of electronic circuits
AssigneeFairchild Semiconductor Corporation
InventorJohn Schinabeck
Life of this patent
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AssigneeFairchild Semiconductor Corporation
InventorJohn Schinabeck
Estimating the term…
A plurality of signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals representing logic states or other parameters onto input pins of the device under test. The responses to the stimuli signals are monitored while the device is being tested. Each signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a device power supply connected to the node for supplying a test bias signal, a comparison circuit connected to the node for indicating the relative magnitude of the test bias signal with respect to the bias level at the node, and a latch circuit responsive to the output signal produced by the comparison circuit. The device power supply is included for providing test bias signals to test power drain during functional testing. The transitions of the device power supply are monitored and latched for providing a record of the power drain of the device being tested. Other features are also disclosed.
A method for continuously applying and monitoring a test bias signal at a node of a device under test including digitally programmed source means having a preselected programmed voltage-current characteristic defined by not-to-exceed voltage rail and current rail levels for supplying a test bias signal to the node, comparison means connected to the node, and means for latching the output signal produced by the comparison means, the method comprising the steps of:
Apparatus for continuously applying and monitoring a test bias signal to a node of a device under test, comprising:
Dependencies are inferred from the claim text.