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US 12,640,718 B1Granted
Glitch-free delay line architecture
AssigneeCadence Design Systems, Inc.
InventorsParth Manishbhai Dodiya, Jitendra Kumar Yadav, Sachin Ramesh Gugwad
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Abstract
Dynamically updating a delay line code. A circuit for updating a delay line code is provided having a delay line having a first chain of interleaved logic gates and a second chain of interleaved logic gates. The circuit further include a first clock path generated based upon the first chain of interleaved logic gates and a second clock path generated based upon the second chain of interleaved logic gates, wherein an output of at least one logic gate is forced to zero prior to performing a code update.
Claims10
A method for updating a delay line code, comprising:
- receiving a strobe input at a delay line;
- receiving a delay cell code at the delay line;
- generating a first clock path based upon a first chain of interleaved logic gates included within the delay line;
- generating a second clock path based upon a second chain of interleaved logic gates included within the delay line, wherein an output of at least one logic gate is forced to zero prior to performing a code update.
1 more element
Dependencies are inferred from the claim text.