Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle

Synchronous clock generator for synchronizing a delayed and inverted synthesized 50% duty cycle clock signal with a reference clock signal, each clock signal having a first and second state transition during each clock period, comprising:

• an inverting controllable delay line with a nominal delay of one half of a period of the reference clock having the synthesized clock signal at its input and a delayed inverted replica at its output;
• a delay line control loop comprising a delay line controller coupled to the inverting controllable delay line for producing at the delay line output an inverted synthesized clock waveform with its first transition synchronous with a corresponding first transition of the reference clock signal, the delay of the delay line controlled by the delay line controller by comparing the reference clock first transition with the inverted synthesized clock signal at the output of the delay line;
• and
• clock waveform generator comprising a clock waveform generator coupled to the inverting controllable delay line for synthesizing a 50% duty cycle clock waveform by using the inverting delay line to produce a half period delayed in an inverted replica of the reference clock first transition to synthesize the second transition of the synthesized waveform.