Duty cycle adjust with independent rising and falling edge control
AssigneeMicron Technology, Inc.
InventorJeremy Robert Kuehlwein
Life of this patent
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Abstract
A signal processing first apparatus includes a first input node configured to receive a first input signal with a first duty cycle. Multiple parallel-coupled inverter circuits can be coupled to the first input node and the first output node, with each inverter circuit including one or more control nodes. The first output node provides a first output signal that is based on the first input signal. A decoder circuit receives a first command signal and provides corresponding inverter control signals to the control nodes of the inverter circuits. Each inverter circuit can independently modify a timing characteristic of the first input signal and contribute to the first output signal.
Claims20
A signal processing apparatus comprising:
- a first input node configured to receive a first input signal having a first duty cycle;
- multiple parallel-coupled inverter circuits coupled to the first input node and to a first output node, wherein each of the inverter circuits comprises a respective control node, and wherein the first output node is configured to provide a first output signal based on the first input signal;
- and
- a decoder circuit configured to receive a first command signal and, in response, provide respective inverter control signals to each of the control nodes of the inverter circuits;
- wherein each of the inverter circuits is independently configured by its corresponding inverter control signal from the decoder circuit to change a timing characteristic of the first input signal and provide a portion of the first output signal.
A method comprising:
- receiving an AC input signal at a first input node of a delay and duty cycle adjust (DADCA) circuit, wherein the DADCA circuit includes multiple parallel-coupled inverter circuits;
- receiving a first command signal;
- in response to the first command signal, selectively configuring each of the parallel-coupled inverter circuits of the DADCA circuit for one of no signal adjustment, duty cycle adjustment, or delay signal processing;
- and
- processing the AC input signal using the parallel-coupled inverter circuits and, in response, providing an output signal at a first output node of the DADCA circuit.
A signal processing circuit comprising:
- a first delay and duty cycle adjustment (DADCA) circuit comprising:
- a first input node configured to receive a first input signal having a first duty cycle;
- and
- a first instance of multiple parallel-coupled inverter circuits coupled to the first input node and to a first output node, wherein each of the inverter circuits comprises a respective pair of control nodes, and wherein the first output node is configured to provide a first output signal based on the first input signal;
- a second delay and duty cycle adjustment (DADCA) circuit comprising:
- a second input node configured to receive a second input signal that is complementary to the first input signal;
- and
- a second instance of multiple parallel-coupled inverter circuits coupled to the second input node and to a second output node, wherein each of the inverter circuits comprises a respective pair of control nodes, and wherein the second output node is configured to provide a second output signal based on the second input signal;
- and
- a decoder circuit configured to receive a first command signal and, in response, provide respective inverter circuit control signals to each of the control nodes in the first and second instances of the multiple parallel-coupled inverter circuits;
- wherein each of the inverter circuits is separately configured by its corresponding control signals from the decoder circuit to change a timing characteristic of the first input signal or the second input signal to provide the first and second output signals.
Dependencies are inferred from the claim text.