Delay Line Unit Circuits and Methods

A method comprising:

• receiving first and second input signals at a first portion of a delay line unit;
• and
• activating a first NMOS device to provide conduction to an outputof the delay line unit, wherein:
• at a second portion of the delay line unit, the first NMOS device is coupled between a reset input and the output;
• and
• the first NMOS device is activated upon receiving the first input signal.

A non-transitory computer-readable medium storing computer-readable code for fabrication of a circuit, comprising:

• one or more delay line units, wherein each of the delay line units comprises:
• a first portion and one or more second portions, wherein:
• the first portion comprises a NAND gate;
• and
• each of the one or more second portions comprises a PMOS device and first, second, and third NMOS devices, and wherein:
• each of the one or more delay line units is configured for an AND gate logic operation.