Programmable delays and methods thereof
AssigneeFerroelectric Memory GmbH
InventorStefano Sivero
Life of this patent
Estimating the term…
Abstract
Disclosed herein is a programmable delay circuit for providing an adjustable delay for a signal transmitted from an input node to an output node. The adjustable delay circuit includes an input node; an output node; and a pair of inverter circuits coupled in series between the input node and the output node, wherein the pair of inverter circuits is configured to provide an adjustable delay for a signal transmitted from the input node to the output node. At least one inverter circuit of the pair of inverter circuits includes a state-programmable memory element that allows the pair of inverter circuits to be configurable between a first delay mode or a second delay mode.
Claims8
A programmable edge delay circuit comprising:
- an input node configured to receive an input signal;
- an output node configured to provide as an output signal a delayed version of the input signal;
- a first inverter circuit connected to the input node, wherein the first inverter circuit comprises a first state-programmable field-effect transistor that is programmable to a first remanent polarization state or a second remanent polarization state different from the first remanent polarization state;
- and
- a second inverter circuit connected between the first inverter circuit and the output node, wherein the second inverter circuit comprises a second state-programmable field-effect transistor that is programmable to the first remanent polarization state or the second remanent polarization state,
- wherein the first state-programmable field-effect transistor is in the first remanent polarization state and the second state-programmable field-effect transistor is in the second remanent polarization state,
- wherein a longer timing delay is provided on one edge of the input signal while providing a shorter delay on the other edge of the input signal.
Dependencies are inferred from the claim text.