G11C 29/1201
Comprising i/o circuitry
Official title: {comprising I/O circuitry}
G11C29/1201 (Comprising i/o circuitry) appears on 1,275 US grants and 1,447 published applications in this corpus.
Search patents in G11C- Granted patents
- 1,275
- Published applications
- 1,447
- Assignees
- 256
- Inventors
- 2,400
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 1 | 0 |
| 1996 | 0 | 0 |
| 1997 | 1 | 0 |
| 1998 | 1 | 0 |
| 1999 | 4 | 0 |
| 2000 | 6 | 0 |
| 2001 | 6 | 3 |
| 2002 | 7 | 10 |
| 2003 | 10 | 13 |
| 2004 | 20 | 31 |
| 2005 | 23 | 51 |
| 2006 | 36 | 79 |
| 2007 | 54 | 61 |
| 2008 | 42 | 67 |
| 2009 | 55 | 86 |
| 2010 | 77 | 35 |
| 2011 | 63 | 40 |
| 2012 | 43 | 28 |
| 2013 | 29 | 29 |
| 2014 | 45 | 44 |
| 2015 | 32 | 37 |
| 2016 | 45 | 35 |
| 2017 | 53 | 57 |
| 2018 | 41 | 48 |
| 2019 | 55 | 60 |
| 2020 | 64 | 59 |
| 2021 | 47 | 69 |
| 2022 | 82 | 101 |
| 2023 | 88 | 99 |
| 2024 | 84 | 107 |
| 2025 | 97 | 96 |
| 2026 | 60 | 102 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Apparatuses and methods for read data preconditioning using a neural network6 Oct 2026US 12,755,804 B2Micron Technology, Inc.
- Semiconductor system for detecting fail location29 Sep 2026US 12,749,551 B2SK hynix Inc.
- Memory controller capable of performing multiple operations, an operation method thereof, a memory device, and a memory system29 Sep 2026US 12,749,553 B2Samsung Electronics Co., Ltd.
- Apparatuses, systems, and methods for per row error scrub information registers8 Sep 2026US 12,731,655 B2Micron Technology, Inc.
- Proactive history read adaptation without test read1 Sep 2026US 12,725,673 B2SK hynix Inc.
- Self-calibration in a memory device8 Oct 2026US 2026/0311791 A1Micron Technology, Inc.
- Scheduling scan operations in memory sub-systems1 Oct 2026US 2026/0301836 A1Micron Technology, Inc.
- Clock generation circuits for memory devices with built-in self test1 Oct 2026US 2026/0301838 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Handling power-loss reset events with bad block risk mitigation1 Oct 2026US 2026/0301840 A1Micron Technology, Inc.
- Memory controller capable of performing multiple operations, an operation method thereof, a memory device, and a memory system1 Oct 2026US 2026/0301842 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Semiconductor memory apparatus and test circuit therefor417US 8,873,272 B2SK hynix Inc. · 2014
- Semiconductor package using terminals formed on a conductive layer of a circuit board258US 6,040,622 ASanDisk Corporation · 2000
- Memory module and memory system151US 7,123,497 B2Elpida Memory, Inc. · 2006
- Semiconductor package using terminals formed on a conductive layer of a circuit board90US 6,410,355 B1SanDisk Corporation · 2002
- Parallel compression test circuit of memory device84US 7,187,195 B2Hynix Semiconductor Inc. · 2007