Back to results
US 7,187,195 B2Granted
Parallel compression test circuit of memory device
AssigneeHynix Semiconductor Inc.
InventorTaek Seung Kim
Life of this patent
Estimating the term…
Abstract
A parallel compression test circuit of a memory device disperses peak current and reduce noise by operating input/output amplifiers at different timings in a parallel compression test mode. The parallel compression test circuit comprises an input/output amplification control unit for activating a plurality of input/output amplifiers connected to a selected bank in a normal mode, and activating the plurality of input/output amplifiers in each bank at different timings in a test mode.
Claims18
A compression test circuit of a memory device, comprising:
- a plurality of banks each comprising a plurality of bit line sense amplifiers for sensing and amplifying data in bit lines;
- a plurality of input/output amplifiers to amplify data which is amplified by the bit line sense amplifier and is loaded in input/output lines;
- a plurality of compression comparators for compressing and comparing data amplified by the plurality of input/output amplifiers in each bank;
- a plurality of global input/output drivers for driving each data amplified by the plurality of input/output amplifiers or for driving each of a plurality of comparison signals outputted from the plurality of compression comparators;
- a plurality of output drivers for driving data driven by the global input/output driving unit to an external pin;
- and
- an input/output amplification control unit for generating a plurality of first control signals to activate the plurality of input/output amplifiers in each bank at different timings in a test mode.
4 more elements
A compression test circuit of a memory device, comprising:
- a plurality of banks each comprising a plurality of bit line sense amplifiers for sensing and amplifying data in bit lines;
- a plurality of input/output amplifiers to amplify data which is amplified by the bit line sense amplifier and is loaded in input/output lines;
- a plurality of compression comparators for compressing and comparing data amplified by the plurality of input/output amplifiers in each bank;
- a plurality of global input/output drivers for driving each data amplified by the plurality of input/output amplifiers or driving each of a plurality of comparison signals outputted from the plurality of compression comparators;
- a plurality of output drivers for driving data driven by the global input/output driving unit to an external pin;
- and
- an input/output amplification control unit for generating a plurality of first control signals to activate the plurality of input/output amplifiers connected to each bank in a test mode by a plurality of groups at different timings.
4 more elements
Dependencies are inferred from the claim text.