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US 12,749,551 B2Granted
Semiconductor system for detecting fail location
AssigneeSK hynix Inc.
InventorDong Yoon Ka
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a memory circuit including a plurality of mats and configured to output first read data having a data sequence identical to a data sequence of pattern data after the start of a read operation during a test operation mode operation and configured to output a fail address including error information of the first read data, and a data processing circuit configured to output the first read data as data and configured to generate fail location information by encoding the fail address.
Claims22
A semiconductor device comprising:
- a memory circuit comprising a plurality of mats and configured to:
- output first read data having a data sequence identical to a data sequence of pattern data after a start of a read operation during a test operation mode operation, which is different from a normal operation;
- and
- output a fail address comprising error information of the first read data when the pattern data is different from the first read data during the test operation mode operation;
- and
- a data processing circuit configured to output the first read data as data and configured to generate fail location information by encoding the fail address.
3 more elements
A semiconductor system comprising:
- a controller configured to output a command address during a data bus inversion operation, configured to receive data, configured to output the command address and pattern data during a test operation mode operation, which is different from a normal operation, and configured to receive fail location information;
- and
- a semiconductor device configured to output second read data as the data by inverting or not inverting the second read data based on a comparison between first read data and second read data after a start of read operations that are consecutively performed during a data bus inversion operation based on the command address, configured to output third read data as the data after the start of the read operation during the test operation mode operation based on the command address, and configured to output a fail address comprising error information of the third read data as the fail location information by encoding the fail address when the third read data and the pattern data are different.
A data output method comprising:
- detecting which of a data bus inversion operation and a test operation mode operation is to be performed based on a command address;
- performing a data bus inversion operation including:
- generating write data by receiving data after a start of a write operation based on the command address, storing the write data in a plurality of mats based on a plurality of mat addresses that are all enabled, and outputting, as the data, first read data and second read data that are output from the write data by one of inverting and not inverting the first read data and the second read data after a start of a read operation;
- and
- performing a test operation mode operation, which is different from a normal operation, including:
- generating the write data by receiving the data identical with pattern data after the start of the write operation based on the command address, storing the write data in the plurality of mats, and outputting, as fail location information, third read data that are output from the write data and a fail address comprising error information of the third read data by encoding the third read data and the fail address after the start of the read operation.
3 more elements
A method comprising:
- comparing first read data and pattern data resulting in comparison data;
- and
- when the first read data is different from the pattern data, performing a test operation mode operation, which is different from a normal operation, including:
- outputting the first read data, outputting a fail address comprising error information of the first read data, and generating fail location information by encoding the fail address.
1 more element
Dependencies are inferred from the claim text.