US 7,123,497 B2 · Memory module and memory system

Abstract

In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, it has become clear that there is a restriction on the transfer rate of the system data signal and that speeding-up cannot be expected. A current consumption in a plurality of DRAMs constituting the memory module is large, and this is also a factor for hindering the speeding-up. There is obtained a memory module in which a plurality of DRAM chips are stacked on an IO chip and in which each DRAM chip is connected to the IO chip by a through electrode and which comprises a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. In this constitution, a wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Claims20

Dependent claims

A memory module comprising:

a system input/output terminal via which a system data signal having a predetermined data width is input/output;
and a plurality of memory chips which transmit/receive an internal data signal broader than the system input/output terminal, the memory module further comprising:
an IO chip including a function of performing conversion between the system data signal and the internal data signal in the system input/output terminal, the plurality of memory chips being stacked on the IO chip and being connected to the IO chip via through electrodes extending through the plurality of stacked memory chips.

Dependencies are inferred from the claim text.

Memory module and memory system

Life of this patent

Memory module and memory system

Life of this patent

Abstract

Claims20