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US 12,731,655 B2Granted
Apparatuses, systems, and methods for per row error scrub information registers
AssigneeMicron Technology, Inc.
InventorSujeet Ayyapureddi
Life of this patent
Estimating the term…
Abstract
Apparatuses, systems, and methods for per row error correct and scrub (pRECS) registers. A mode register may include a pRECS enable register, to enable a pRECS mode. When the prECS mode is enabled, pRECS information associated with each row may be collected which reflects a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row. A pRECS address register may specify a location in the memory array to store the pRECS information.
Claims21
An apparatus, comprising:
- a memory array comprising a first plurality of memory cells at the intersection of a first word line and a plurality of bit lines and a second plurality of memory cells at the intersection of a second word line and the plurality of bit lines, wherein a first plurality of codewords are stored in at least some of the first plurality of memory cells and a second plurality of codewords are stored in at least some of the second plurality of memory cells;
- a mode register configured to store a per-row error correct and scrub (ECS) count enable signal;
- and
- ECS logic configured to:
- count a first number of the first plurality of codewords along the first word line which contain an error when the per-row ECS count enable signal is active;
- count a second number of the second plurality of codewords along the second word line which contain an error when the per-row ECS count enable signal is active;
- collect other ECS information, the other ECS information including a third number of the first plurality of codewords and the second plurality of codewords which include errors regardless of whether the per-row ECS count enable signal is active or not, the other ECS information comprising at least one of an error count (EC) count value or an errors per row count (EpRC) count value;
- and
- store the first number in the memory array.
6 more elements
An apparatus, comprising:
- a memory array comprising a first plurality of memory cells at the intersection of a first word line and a plurality of bit lines and a second plurality of memory cells at the intersection of a second word line and the plurality of bit lines, wherein a first plurality of codewords is stored in at least some of the first plurality of memory cells and a second plurality of codewords is stored in at least some of the second plurality of memory cells;
- a mode register configured to store a per-row error correct and scrub (ECS) count enable signal;
- and
- ECS logic configured to:
- count a first number of the first plurality of codewords along the first word line which contain an error when the per-row ECS count enable signal is active;
- count a second number of the second plurality of codewords along the second word line which contain an error when the per-row ECS count enable signal is active;
- and
- store the first number in one or more stranded columns of the memory array, wherein the one or more stranded columns are configured as non-addressable memory in at least a mode of the apparatus.
5 more elements
An apparatus, comprising:
- a memory array comprising a first plurality of memory cells at the intersection of a first word line and a plurality of bit lines and a second plurality of memory cells at the intersection of a second word line and the plurality of bit lines, wherein a first plurality of codewords is stored in at least some of the first plurality of memory cells and a second plurality of codewords is stored in at least some of the second plurality of memory cells;
- a mode register configured to store a per-row error correct and scrub (ECS) count enable signal;
- and
- ECS logic configured to:
- count a first number of the first plurality of codewords along the first word line which contain an error when the per-row ECS count enable signal is active;
- count a second number of the second plurality of codewords along the second word line which contain an error when the per-row ECS count enable signal is active;
- and
- store the first number in the memory array, wherein:
- a first portion of the plurality of memory cells is used to store data;
- a second portion of the plurality of memory cells is used to store metadata associated with the data;
- a third portion of the plurality of memory cells is used neither for data or metadata;
- and
- the ECS logic is configured to store the first number in the third portion, wherein the mode register is configured to store a per-row ECS address that specifies selected ones of the plurality of memory cells used to store the first number.
10 more elements
An apparatus, comprising:
- a memory array comprising a first plurality of memory cells at the intersection of a first word line and a plurality of bit lines and a second plurality of memory cells at the intersection of a second word line and the plurality of bit lines, wherein a first plurality of codewords is stored in at least some of the first plurality of memory cells and a second plurality of codewords is stored in at least some of the second plurality of memory cells;
- a mode register configured to store a per-row error correct and scrub (ECS) count enable signal;
- and
- ECS logic configured to:
- count a first number of the first plurality of codewords along the first word line which contain an error when the per-row ECS count enable signal is active;
- and
- count a second number of the second plurality of codewords along the second word line which contain an error when the per-row ECS count enable signal is active,
- wherein:
- a first portion of the first plurality of memory cells is used to store data;
- a second portion of the first plurality of memory cells is used to store metadata associated with the data;
- a third portion of the first plurality of memory cells is used neither for data or metadata, and
- the ECS logic is configured to store the first number in the third portion.
9 more elements
An apparatus, comprising:
- a memory array comprising a first plurality of memory cells at the intersection of a first word line and a plurality of bit lines and a second plurality of memory cells at the intersection of a second word line and the plurality of bit lines, wherein a first plurality of codewords is stored in at least some of the first plurality of memory cells and a second plurality of codewords is stored in at least some of the second plurality of memory cells;
- a mode register configured to store a per-row error correct and scrub (ECS) count enable signal;
- and
- ECS logic configured to:
- count a first number of the first plurality of codewords along the first word line which contain an error when the per-row ECS count enable signal is active;
- count a second number of the second plurality of codewords along the second word line which contain an error when the per-row ECS count enable signal is active;
- and
- store the first number and the second number in one or more stranded columns of the memory array, wherein the one or more stranded columns are configured as non-addressable memory in at least one mode of the apparatus.
5 more elements
Dependencies are inferred from the claim text.