G11C 2207/229
Timing of a write operation
G11C2207/229 (Timing of a write operation) appears on 375 US grants and 343 published applications in this corpus.
Search patents in G11C- Granted patents
- 375
- Published applications
- 343
- Assignees
- 97
- Inventors
- 535
- Latest grant
- 22 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2000 | 15 | 0 |
| 2001 | 11 | 2 |
| 2002 | 12 | 9 |
| 2003 | 19 | 31 |
| 2004 | 26 | 38 |
| 2005 | 28 | 24 |
| 2006 | 22 | 12 |
| 2007 | 14 | 10 |
| 2008 | 13 | 8 |
| 2009 | 5 | 3 |
| 2010 | 8 | 3 |
| 2011 | 4 | 4 |
| 2012 | 4 | 5 |
| 2013 | 7 | 6 |
| 2014 | 4 | 6 |
| 2015 | 7 | 5 |
| 2016 | 10 | 13 |
| 2017 | 16 | 19 |
| 2018 | 19 | 17 |
| 2019 | 21 | 26 |
| 2020 | 30 | 24 |
| 2021 | 17 | 29 |
| 2022 | 24 | 13 |
| 2023 | 14 | 17 |
| 2024 | 12 | 8 |
| 2025 | 9 | 6 |
| 2026 | 4 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Apparatuses, systems, and methods for data timing alignment with fast alignment mode22 Sep 2026US 12,744,074 B2Micron Technology, Inc.
- Memory device and memory controller configured to perform re-training based on temperature information and electronic device including the same16 Jun 2026US 12,658,242 B2Samsung Electronics Co., Ltd.
- Semiconductor memory device including memory string and plurality of select transitstors and method including a write operation12 May 2026US 12,626,738 B2Kioxia Corporation
- Method and apparatus to reduce time to program single level cell blocks in a non-volatile memory6 Jan 2026US 12,518,833 B2Intel NDTM US LLC
- Apparatuses, systems, and methods for error correction11 Nov 2025US 12,469,575 B2
- Semiconductor memory device including memory string and plurality of select transitstors and method including a write operation20 Aug 2026US 2026/0245604 A1Kioxia Corporation
- Method and apparatus to reduce time to program single level cell blocks in a non-volatile memory14 May 2026US 2026/0134924 A1Intel NDTM US LLC
- Memory device and operation method thereof7 May 2026US 2026/0128069 A1Winbond Electronics Corp.
- Semiconductor devices capable of performing write training without read training, and memory system including the same5 Feb 2026US 2026/0038550 A1Samsung Electronics Co., Ltd.
- Apparatuses, systems, and methods for error correction5 Feb 2026US 2026/0038620 A1Lodestar Licensing Group LLC
Most cited
By later US patents
- Method and apparatus for accessing a memory device430US 6,157,578 ASTMicroelectronics S.r. l. · 2000
- High speed DRAM architecture with uniform access latency419US 8,503,250 B2Mosaid Technologies Incorporated · 2013
- Merging write cycles by comparing at least a portion of the respective write cycle addresses296US 6,356,485 B1Integrated Device Technology, Inc. · 2002
- Memory access system and method using de-coupled read and write circuits193US 7,466,607 B2Analog Devices, Inc. · 2008
- Semiconductor memory device with floating storage bulk region and method of manufacturing the same180US 6,621,725 B2Kabushiki Kaisha Toshiba · 2003