US 6,621,725 B2 · Semiconductor memory device with floating storage bulk region and method of manufacturing the same

Abstract

A memory cell MC comprises one MOS transistor having a floating bulk region which is electrically isolated from others. A gate electrode 13 of the MOS transistor is connected to a word line WL, a drain diffusion region 14 thereof is connected to a bit line BL, and a source diffusion region 15 thereof is connected to a fixed potential line SL. The memory cell stores a first threshold state in which majority carriers produced by impact ionization are injected and held in the bulk region 12 of the MOS transistor and a second threshold state in which the majority carriers in the bulk region 12 of the MOS transistor are emitted by a forward bias at a pn junction on the drain side as binary data. Thereby, a semiconductor memory device in which a simple transistor structure is used as a memory cell, enabling dynamic storage of binary data by a small number of signal lines can be provided.

Claims23

Dependent claims

A semiconductor memory device including at least one transistor, wherein the transistor comprises:

a semiconductor layer which is a first conduction type and electrically isolated from other memory cells to get floating;
a drain diffusion region which is a second conduction type, formed in the first conduction-type semiconductor layer, and connected to a bit line;
a source diffusion region which is the second conduction type, formed apart from the drain diffusion region in the first conduction-type semiconductor layer, and connected to a source line;
and
a gate electrode which is formed on the semiconductor layer between the drain diffusion region and the source diffusion region with a gate insulator therebetween, and forms a word line;
wherein the transistor has a first data state having a first threshold voltage in which excessive majority carriers are held in the semiconductor layer and a second data state having a second threshold voltage in which the excessive majority carriers in the semiconductor layer are emitted.

3 more elements

A semiconductor memory device comprising:

an SOI substrate in which a silicon layer is formed on an insulating film formed on a silicon substrate;
a plurality of transistors which have drain diffusion regions and source diffusion regions formed in the silicon layer and gate electrodes formed on the silicon layer, pairs of the transistors, each pair sharing one of the drain diffusion regions, being arranged in a matrix form with element-isolated in a channel width direction, wherein the gate electrodes of the transistors arranged in a first direction are continuously formed so as to constitute word lines;
and
a plurality of bit lines running in a second direction intersecting the first direction and connected to the drain diffusion regions of the transistors;
wherein each of the transistor has a first data state having a first threshold voltage in which excessive majority carriers are held in the silicon layer and a second data state having a second threshold voltage in which the excessive majority carriers in the silicon layer are emitted.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device with floating storage bulk region and method of manufacturing the same

Life of this patent

Semiconductor memory device with floating storage bulk region and method of manufacturing the same

Life of this patent

Abstract

Claims23