High speed DRAM architecture with uniform access latency
AssigneeMosaid Technologies Incorporated
InventorPaul Demone
Life of this patent
Estimating the term…
Abstract
A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
Claims19
A method of reading data in a Dynamic Random Access Memory (DRAM), the method comprising:
- receiving a read command and an address on a first edge of a control signal;
- activating a bit line equalization circuit and deactivating a word line enable device on the first edge of the control signal;
- activating the word line enable device for selecting a word line according to the address after a first delay from the first edge of the control signal;
- activating a sense amplifier coupled to a bit line pair for sensing data in a memory cell coupled to the word line and to the bit line pair after the first delay plus a second delay from the first edge of the control signal;
- and
- deactivating the word line enable device for de-selecting the word line on a second edge of the control signal.
Dependencies are inferred from the claim text.