Memory access system and method using de-coupled read and write circuits
AssigneeAnalog Devices, Inc.
InventorsPaul W. Hollis, George M. Lattimore, Matthew B. Rutledge
Life of this patent
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Abstract
A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.
Claims27
A de-coupled memory access system comprising:
- a memory access control circuit configured to generate first and second independent, de-coupled time references, said memory access control circuit including:
- a read initiate circuit responsive to said first time reference and a read signal for generating a read enable signal, and
- a write initiate circuit responsive to said second time reference and a write signal for generating a write enable signal independent of said read enable signal for providing independent, de-coupled write access to a memory array to independently generate the read enable signal in relation to the write enable signal to increase the time allowed for a read access in each cycle, in which there is a single read enable signal or a single write enable signal in each cycle.
A de-coupled read and write memory access method, the method comprising the steps of:
- providing first and second time reference signals from a memory access control circuit;
- generating a read enable signal from the memory access control circuit to access a memory array in response to said first time reference and a read initialization signal;
- and
- generating a write enable signal from a memory access control circuit, independent of said read enable signal in response to said second time reference and a write signal to provide independent, de-coupled write access to said memory array to independently generate the read enable signal in relation to the write enable signal to increase the time allowed for a read access in each cycle, in which there is a single read enable signal or a single write enable signal in each cycle.
Dependencies are inferred from the claim text.