Apparatuses, systems, and methods for error correction
OwnerKeisuke Fujishiro, Yoshifumi Mochidainventors
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Abstract
Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.
Claims20
A method comprising:
- receiving a read command;
- responsive to the read command, providing a plurality of bits and a parity bit from a memory array to an error correction code (ECC) circuit comprising a read path and a write path;
- storing the parity bit in a latch of the read path;
- generating an encoded bit based on the plurality of bits with a logic tree shared by the read path and the write path;
- and
- comparing the parity bit to the encoded bit.
A method comprising:
- receiving a write command;
- receiving a plurality of bits associated with the write command;
- generating an encoded bit based on a portion of the plurality of bits with a logic tree of an error correction code (ECC) circuit comprising a read path and a write path, wherein the logic tree is shared by the read path and the write path;
- storing the encoded bit in a latch;
- and
- writing, in parallel, the plurality of bits and the encoded bit to a memory array.
A memory device comprising:
- an error correction code (ECC) circuit comprising a read path and a write path, the ECC circuit further comprising:
- a logic tree shared by the read path and the write path configured to generate an encoded bit based on a plurality of data bits;
- a first latch in the read path configured to store a parity bit associated with a plurality of read data bits;
- and
- a second latch in the write path configured to store the encoded bit associated with a plurality of write data bits.
Dependencies are inferred from the claim text.