Method and apparatus to reduce time to program single level cell blocks in a non-volatile memory

A system comprising:

• a memory controller;
• and
• a NAND device coupled with the memory controller, the NAND device comprising:
• a memory array, the memory array including a plurality of blocks of NAND cells;
• and
• circuitry including a memory to store a plurality of parameters associated with a first program operation to program NAND cells in the memory array, wherein the circuitry is configured to:
• implement the first program operation including a full first stage operation;
• determine the plurality of parameters, for programming the NAND cells, based on the first program operation;
• and
• perform an ordered sequence of second program operations including at least two different types of first stages implemented using the plurality of parameters, wherein a respective second program operation has a lower read and program latency of than the first program operation.