Merging write cycles by comparing at least a portion of the respective write cycle addresses

An integrated circuit comprising:

• a memory array including a plurality of memory cells;
• write queue means for storing at least address information for at least one pending internal write operation;
• means for determining whether a first group of memory cells to be otherwise written by a pending internal write operation and a second group of memory cells to be otherwise written by another internal write operation corresponding to a subsequently-received write cycle request may instead be both written using a single internal write operation;
• means for merging write data associated with the subsequently-received write cycle request into, and superseding any commonly-addressed data bits of, write data associated with the pending internal write operation;
• and
• means for performing a single internal write operation to write the merged data rather than two separate internal write operations.

In an integrated circuit having a memory array and containing a write queue for storing at least address information associated with at least one pending internal write operation into the memory array, a method of operating the integrated circuit comprising:

• determining whether a first group of memory cells to be otherwise written by a pending internal write operation and a second group of memory cells to be otherwise written by another internal write operation corresponding to a subsequently-received write cycle request may instead be both written using a single internal write operation;
• and if so, then
• merging write data associated with the subsequently-received write cycle request into, and superseding any commonly-addressed data bits of, write data associated with the pending internal write operation;
• and
• performing a single internal write operation to write the merged data into the memory array.

In an integrated circuit having a memory array and containing a write queue for storing at least address information associated with at least one pending internal write operation into the memory array, a method of operating the integrated circuit comprising:

• comparing at least a portion of the address information associated with a pending internal write operation stored within the write queue to corresponding address information associated with a subsequently-received write cycle request to determine whether a first group of memory cells to be otherwise written by the pending internal write operation and a second group of memory cells to be otherwise written by another internal write operation corresponding to a subsequently-received write cycle request may instead be both written using a single internal write operation;
• if so, then
• skipping the pending internal write operation;
• merging write data associated with the subsequently-received write cycle request into, and superseding any commonly-addressed data bits of, write data associated with the pending internal write operation;
• and
• performing a single internal write operation to write the merged data;
• if not so, then
• performing the pending internal write operation in its normal order;
• and then
• performing another internal write operation to write data associated with the subsequently-received write cycle request.