G11C 2029/0401
In embedded memories
Official title: {in embedded memories}
G11C2029/0401 (In embedded memories) appears on 557 US grants and 540 published applications in this corpus.
Search patents in G11C- Granted patents
- 557
- Published applications
- 540
- Assignees
- 201
- Inventors
- 1,136
- Latest grant
- 18 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1997 | 3 | 0 |
| 1998 | 1 | 0 |
| 1999 | 1 | 0 |
| 2000 | 5 | 0 |
| 2001 | 3 | 7 |
| 2002 | 8 | 8 |
| 2003 | 8 | 10 |
| 2004 | 17 | 28 |
| 2005 | 17 | 45 |
| 2006 | 26 | 33 |
| 2007 | 32 | 34 |
| 2008 | 42 | 35 |
| 2009 | 34 | 27 |
| 2010 | 36 | 26 |
| 2011 | 36 | 22 |
| 2012 | 28 | 16 |
| 2013 | 31 | 32 |
| 2014 | 19 | 34 |
| 2015 | 31 | 20 |
| 2016 | 15 | 20 |
| 2017 | 21 | 12 |
| 2018 | 16 | 28 |
| 2019 | 31 | 24 |
| 2020 | 22 | 16 |
| 2021 | 15 | 22 |
| 2022 | 22 | 9 |
| 2023 | 11 | 12 |
| 2024 | 11 | 9 |
| 2025 | 9 | 9 |
| 2026 | 6 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Flash memory architecture implementing interconnection redundancy18 Aug 2026US 12,711,028 B2
- Method for performing aging test on semiconductor used for neural network16 Jun 2026US 12,658,280 B2Deepx Co., Ltd.
- Temperature control for multiple die types in a common package9 Jun 2026US 12,651,615 B2Cisco Technology, Inc.
- Data processing apparatus, memory failure determination method, and non-transitory computer readable recording medium14 Apr 2026US 12,602,284 B2Yokogawa Electric Corporation
- Self-repairable chip for silent data corruption issues14 Apr 2026US 12,602,298 B2Google Inc.
- Solder mask fault fiber optics sensor14 May 2026US 2026/0136456 A1Micron Technology, Inc.
- Hybrid built-in system test switching circuitry for embedded memory testing5 Mar 2026US 2026/0066023 A1STMicroelectronics International N. V.
- Self-Repairable Chip For Silent Data Corruption Issues2 Oct 2025US 2025/0307090 A1Google Inc.
- Computer-implemented method for testing logic circuit implementing the cache function21 Aug 2025US 2025/0266117 A1STMicroelectronics International N. V.
- Memory bist circuit and method3 Jul 2025US 2025/0218524 A1Texas Instruments Incorporated
Most cited
By later US patents
- Multi-chip package having repairable embedded memories on a system chip with an EEPROM chip storing repair information161US 7,053,470 B1Azul Systems, Inc. · 2006
- Fault-tolerant hierarchical bus system and method of operating same138US 5,666,480 AMonolithic System Technology, Inc. · 1997
- Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system126US 5,592,632 AMonolithic System Technology, Inc. · 1997
- Method and system for flexible control of BIST registers based upon on-chip events109US 6,374,370 B1Hewlett-Packard Company · 2002
- Method and circuit for communication between a module and a bus controller in a wafer-scale integrated circuit system89US 5,613,077 AMonolithic System Technology, Inc. · 1997