US 7,053,470 B1Granted

Multi-chip package having repairable embedded memories on a system chip with an EEPROM chip storing repair information

AssigneeAzul Systems, Inc.

InventorsScott D. Sellers, Elias Atmeh

Life of this patent

Estimating the term…

Loading patent…

Abstract

A die with embedded memory is packaged together in a same dual-chip package with an EEPROM die. Defects in the embedded memory can be repaired using redundant rows or columns. A built-in self-test (BIST) controller locates defects and a repair image is generated. The repair image is stored in non-volatile memory in the EEPROM die. At power-up, the repair image is copied from the EEPROM die to a volatile repair RAM in the embedded memory die. The redundant rows or columns are mapped to replace defective rows/columns using the repair image in the volatile repair RAM. Although the embedded-memory die has only volatile memory and no fuses, its embedded memory can be repaired using the repair map from the non-volatile EEPROM die. Since the EEPROM die is in the same dual-chip package as the embedded memory die, the repair map is always available.

Claims17

Dependent claims

A packaged system with a repairable embedded memory comprising:

a multi-chip package having external pins for connecting to an external printed-circuit board (PCB);
an embedded memory die packaged within the multi-chip package and electrically connected to a first subset of the external pins;
an embedded memory array on the embedded memory die, the embedded memory array losing data when power is removed from the packaged system;
a non-volatile memory die packaged within the multi-chip package and electrically connected to a second subset of the external pins;
a persistent repair memory within the non-volatile memory die, the persistent repair memory retaining repair data when power is removed from the packaged system;
a volatile repair memory within the embedded memory die, the volatile repair memory receiving repair data originally stored in the persistent repair memory after power-up, but the volatile repair memory losing the repair data when power is removed from the packaged system;
and
a repair controller, coupled to read and use the repair data from the volatile repair memory to repair defective memory locations within the embedded memory array,
whereby defective memory locations in the embedded memory die are repaired using repair data stored in the persistent repair memory that is packaged in a same multi-chip package with the embedded memory die.

6 more elements

A repairable semiconductor device comprising:

an embedded memory die having logic and an embedded memory that loses data when power is removed;
a non-volatile memory die having a non-volatile memory that retains repair data when power is removed;
multi-chip package means for encapsulating the embedded memory die together with the non-volatile memory die in a single package;
redundant memory means for replacing faulty memory locations in the embedded memory;
repair controller means, receiving repair data, for mapping addresses to the embedded memory for faulty memory locations to the redundant memory means, wherein mapping addresses is in response to the repair data;
and
built-in self-test (BIST) means, activated during a test mode, for generating addresses and test data for storage in the embedded memory, and for comparing test data stored in the embedded memory to expected test data to identify the faulty memory locations;
wherein the repair data stored in the non-volatile memory die is generated in response to the faulty memory locations identified by the BIST means and is transferred from the non-volatile memory die to the repair controller means in the embedded memory die after power-up,
whereby repair data is stored in the non-volatile memory die for repairing the embedded memory die that are packaged together in the multi-chip package means.

6 more elements

Dependencies are inferred from the claim text.