Method and system for flexible control of BIST registers based upon on-chip events

A method of debugging and monitoring the performance of a microprocessor, comprising the steps of:

• defining an event by configuring an on-chip state machine to detect when a combination of state machine inputs is asserted, said combination of state machine inputs corresponding to said event, wherein said event may occur at any time during operation of the microprocessor and wherein the combination of state machine inputs may be asserted at any place on the microprocessor;
• defining an action to be taken when said event occurs by configuring said on-chip state machine to drive control information onto a state machine output bus when said event occurs, said control information corresponding to said action;
• executing instructions on said microprocessor until said event occurs;
• and
• in response to said event occurring, controlling one or more signature analysis elements of the microprocessor with the control information to perform signature analysis on a plurality of signals.

A method of debugging and monitoring the performance of a microprocessor, comprising the steps of:

• defining an event by configuring an on-chip state machine to detect when a combination of state machine inputs is asserted, said combination of state machine inputs corresponding to said event, wherein said event may occur at any time during operation of the microprocessor and wherein the combination of state machine inputs may be asserted at any place on the microprocessor;
• defining an action to be taken when said event occurs by configuring said on-chip state machine to drive control information onto a state machine output bus when said event occurs, said control information corresponding to said action;
• executing instructions on said microprocessor until said event occurs;
• and
• in response to said event occurring, controlling one or more recording elements of the microprocessor with the control information to record a plurality of signals.

Apparatus for debugging and monitoring the performance of a microprocessor, comprising:

• one or more memory arrays of the microprocessor;
• a debug block of the microprocessor coupled to the memory arrays that drives control information onto a state machine output bus in response to an event, wherein said event may occur at any time during operation of the microprocessor;
• and
• one or more built-in-self-test (BIST) engines of the microprocessor coupled to the debug block and the one or more memory arrays,
• wherein in response to the event occurring, the control information controls one or more monitor-and-debug elements of the one or more BIST engines to perform one or more monitor or debug operations.